Reset and clock control (RCC) peripheral module. More...

#include <Imt.Base.HAL.STM32H730/Peripherals/RCC.h>

Classes
struct	ClockConfigStruct
	RCC System, AHB and APB busses clock configuration structure. More...

struct	OscillatorConfigStruct
	RCC Oscillator configuration structure definition. More...

struct	PLLConfigStruct
	PLL (phase locked loop) configuration structure definition. More...

Public Types
enum class	PeripheralModule { DMA1 , DMA2 , ADC12 , ETH1MAC , ETH1TX , ETH1RX , USB1OTGHS , USB1OTGHSULPI , DCMI_PSSI , CRYPT , HASH , RNG , SDMMC2 , FMAC , CORDIC , SRAM1 , SRAM2 , MDMA , DMA2D , FMC , OCTOSPI1 , SDMMC1 , OCTOSPI2 , IOMNGR , OTFD1 , OTFD2 , GPIOA , GPIOB , GPIOC , GPIOD , GPIOE , GPIOF , GPIOG , GPIOH , GPIOJ , GPIOK , CRC , BDMA , ADC3 , HSEM , BKPRAM , TIM2 , TIM3 , TIM4 , TIM5 , TIM6 , TIM7 , TIM12 , TIM13 , TIM14 , LPTIM1 , SPI2 , SPI3 , SPDIFRX , USART2 , USART3 , UART4 , UART5 , I2C1 , I2C2 , I2C3 , I2C5 , CEC , DAC12 , UART7 , UART8 , CRS , SWPMI , OPAMP , MDIOS , FDCAN , TIM23 , TIM24 , TIM1 , TIM8 , USART1 , USART6 , UART9 , USART10 , SPI1 , SPI4 , TIM15 , TIM16 , TIM17 , SPI5 , SAI1 , DFSDM1 , LTDC , WWDG1 , SYSCFG , LPUART1 , SPI6 , I2C4 , LPTIM2 , LPTIM3 , LPTIM4 , LPTIM5 , COMP12 , VREF , RTCAPB , SAI4 , DTS }
	Enumeration of all avalibale peripheral modules. More...

enum class	OscillatorType { None , HSE , HSI , LSE , LSI }
	Enumeration for Oscillator type. More...

enum class	OscillatorState { Off , On , Bypass , Calibration }
	Enumeration for OscillatorState. More...

enum class	PLLState { None , Off , On }
	Enumeration for PLL Configuration. More...

enum class	PLLID { PLL1 , PLL2 , PLL3 }
	Enumeration for PLL Configuration. More...

enum class	PLLClockSource { HSI = 0x00U , CSI = 0x01U , HSE = 0x02U , No = 0x03U }
	Enumeration for PLL Clock Source Configuration Chapter 8.7.10, RCC_PLLCSELR Bit 1:0 PLLSRC. More...

enum class	SystemClockType { CPU = 0x01U , SYSCLK = 0x02U , HCLK = 0x04U , PCLK1 = 0x08U , PCLK2 = 0x16U , PCLK3 = 0x32U , PCLK4 = 0x64U }
	Enumeration for system clock type Configuration. More...

enum class	SystemClockSource { HSI = 0x00U , CSI = 0x01U , HSE = 0x02U , PLL1 = 0x03U }
	Enumeration for system Clock Source Configuration Chapter 8.7.6, RCC_CFGR Bits 2:0 SW. More...

enum class	AHBClockDivider { AHB_DIV1 = 0x0U , AHB_DIV2 = 0x8U , AHB_DIV4 = 0x9U , AHB_DIV8 = 0xAU , AHB_DIV16 = 0xBU , AHB_DIV64 = 0xCU , AHB_DIV128 = 0xDU , AHB_DIV256 = 0xEU , AHB_DIV512 = 0xFU }
	Enumeration for AHB clock divider Chapter 8.7.7, RCC_D1CFGR Bits 3:1 HPRE. More...

enum class	APBxClockDivider { APB_DIV1 = 0x0U , APB_DIV2 = 0x4U , APB_DIV4 = 0x5U , APB_DIV8 = 0x6U , APB_DIV16 = 0x7U }
	Enumeration for APB1 and APB2 clock divider Chapter 8.7.7, 8.7.8 and 8.7.9 D1PPRE Bits 6:4, D2PPRE1 Bits 6:4, D2PPRE2 Bits 10:8 and D3PRE Bits 6:5. More...

enum class	RTCSource { LSE = 0x01U , LSI = 0x02U , HSE = 0x03U }
	Enumeration for possible RTC sources. More...

enum class	I2CClockSource { PCLK1 , pll3 , HSI , CSI }
	I2C clock source selection Chapter 8.7.20 & 8.7.21. More...

enum class	PllSaiDivR { Div2 , Div4 , Div8 , Div16 }
	PLLSAI division factor for LCD_CLK. More...

enum class	ClockMux { FMC , OCTOSPI , SDMMC , CKPER , SAI1 , SPI123 , SPI45 , SPDIFRX , DFSDM1 , FDCAN , SWPMI , USART234578 , USART16910 , RNG , I2C1235 , USB , CEC , LPTIM1 , LPUART1 , I2C4 , LPTIM2 , LPTIM345 , ADC , SAI4A , SAI4B , SPI6 }
	Enumeration for Clock Mux. More...

enum class	ClockSource { SYSCLK , LSE , LSI , HSE , HSI , HSI48 , CSI , PLL1R , PLL1Q , PLL1P , PLL2R , PLL2Q , PLL2P , PLL3R , PLL3Q , PLL3P , HCLK1 , HCLK2 , HCLK3 , PCLK1 , PCLK2 , PCLK3 , PCLK4 , PER_CK , I2S_CKIN , SPDIF }
	Enumeration for Clock Source. More...

Static Public Member Functions
static void	enablePeripheralClock (const PeripheralModule module, const bool enabled)
	Enables or disables the High Speed peripheral clock for the given module. More...

static void	resetPeripheralClock (const PeripheralModule module, const bool reset)
	Enables or disables the reset flag for the given module. More...

static bool	configureOscillator (const OscillatorConfigStruct &oscConfig)
	Initializes the RCC Oscillators according to the specified parameters. More...

static bool	configureClock (const ClockConfigStruct &clockConfig, const FLASH::Latency flashLatency)
	Initializes the CPU, AHB and APB busses clocks according to the specified parameters. More...

static bool	configureRtc (const RTCSource rtcSource, const bool doEnable)
	Initializes the CPU, AHB and APB busses clocks according to the specified parameters. More...

static bool	configureRtc (const RTCSource rtcSource, const bool doEnable, uint8_t divisorHSE)

static void	resetBDCR (void)
	Resets the BDC Register, so new values can be written into it. More...

static bool	configureClockMux (const ClockMux clockMux, const ClockSource source)
	Initializes the CPU, AHB and APB busses clocks according to the specified parameters. More...

static void	enableClockSecuritySystem ()
	Enables the clock security system which triggers an NMI interrupt when the HSE fails. More...

static void	clearClockSecurityFailureFlag ()
	Clears the CSS flag to not have an indefnite NMI irq. More...

static void	clearResetFlags ()
	Reset the reset flag of the RCC register. More...

static bool	didWatchdogReset ()
	Checks if the reason for the reset was the independent watchdog. More...

static bool	isLseReady ()
	Returns if the LSE is running and ready. More...

static bool	isLsiReady ()
	Returns if the LSI is running and ready. More...

Detailed Description

Reset and clock control (RCC) peripheral module.

Reference: ST_CortexM7_STM32F767_TRM_Rev4.pdf Chapter 5

Member Enumeration Documentation

◆ AHBClockDivider

enum imt::base::hal::stm32h730::peripherals::RCC::AHBClockDivider

strong

Enumeration for AHB clock divider Chapter 8.7.7, RCC_D1CFGR Bits 3:1 HPRE.

Enumerator
AHB_DIV1	0xxx: system clock not divided
AHB_DIV2	1000: system clock divided by 2
AHB_DIV4	1001: system clock divided by 4
AHB_DIV8	1010: system clock divided by 8
AHB_DIV16	1011: system clock divided by 16
AHB_DIV64	1100: system clock divided by 64
AHB_DIV128	1101: system clock divided by 128
AHB_DIV256	1110: system clock divided by 256
AHB_DIV512	1111: system clock divided by 512

◆ APBxClockDivider

enum imt::base::hal::stm32h730::peripherals::RCC::APBxClockDivider

strong

Enumeration for APB1 and APB2 clock divider Chapter 8.7.7, 8.7.8 and 8.7.9 D1PPRE Bits 6:4, D2PPRE1 Bits 6:4, D2PPRE2 Bits 10:8 and D3PRE Bits 6:5.

Enumerator
APB_DIV1	0xx: AHB clock not divided
APB_DIV2	100: AHB clock divided by 2
APB_DIV4	101: AHB clock divided by 4
APB_DIV8	110: AHB clock divided by 8
APB_DIV16	111: AHB clock divided by 16

◆ ClockMux

enum imt::base::hal::stm32h730::peripherals::RCC::ClockMux

strong

Enumeration for Clock Mux.

Enumerator
FMC
OCTOSPI
SDMMC
CKPER
SAI1
SPI123
SPI45
SPDIFRX
DFSDM1
FDCAN
SWPMI
USART234578
USART16910
RNG
I2C1235
USB
CEC
LPTIM1
LPUART1
I2C4
LPTIM2
LPTIM345
ADC
SAI4A
SAI4B
SPI6

◆ ClockSource

enum imt::base::hal::stm32h730::peripherals::RCC::ClockSource

strong

Enumeration for Clock Source.

Enumerator
SYSCLK
LSE
LSI
HSE
HSI
HSI48
CSI
PLL1R
PLL1Q
PLL1P
PLL2R
PLL2Q
PLL2P
PLL3R
PLL3Q
PLL3P
HCLK1
HCLK2
HCLK3
PCLK1
PCLK2
PCLK3
PCLK4
PER_CK
I2S_CKIN
SPDIF

◆ I2CClockSource

enum imt::base::hal::stm32h730::peripherals::RCC::I2CClockSource

strong

I2C clock source selection Chapter 8.7.20 & 8.7.21.

Enumerator
PCLK1	00 : PCLK1 clock is selected as kernel clock (default after reset)
pll3	01 : pll3 clock is selected as kernel clock
HSI	10 : HSI clock is selected as kernel clock
CSI	11 : CSI clock is selected as kernel clock

◆ OscillatorState

enum imt::base::hal::stm32h730::peripherals::RCC::OscillatorState

strong

Enumeration for OscillatorState.

Enumerator
Off
On
Bypass
Calibration

◆ OscillatorType

enum imt::base::hal::stm32h730::peripherals::RCC::OscillatorType

strong

Enumeration for Oscillator type.

Enumerator
None
HSE
HSI
LSE
LSI

◆ PeripheralModule

enum imt::base::hal::stm32h730::peripherals::RCC::PeripheralModule

strong

Enumeration of all avalibale peripheral modules.

AHB1-4 BUS, APB11-4 BUS

Enumerator
DMA1
DMA2
ADC12
ETH1MAC
ETH1TX
ETH1RX
USB1OTGHS
USB1OTGHSULPI
DCMI_PSSI
CRYPT
HASH
RNG
SDMMC2
FMAC
CORDIC
SRAM1
SRAM2
MDMA
DMA2D
FMC
OCTOSPI1
SDMMC1
OCTOSPI2
IOMNGR
OTFD1
OTFD2
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
GPIOH
GPIOJ
GPIOK
CRC
BDMA
ADC3
HSEM
BKPRAM
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
TIM12
TIM13
TIM14
LPTIM1
SPI2
SPI3
SPDIFRX
USART2
USART3
UART4
UART5
I2C1
I2C2
I2C3
I2C5
CEC
DAC12
UART7
UART8
CRS
SWPMI
OPAMP
MDIOS
FDCAN
TIM23
TIM24
TIM1
TIM8
USART1
USART6
UART9
USART10
SPI1
SPI4
TIM15
TIM16
TIM17
SPI5
SAI1
DFSDM1
LTDC
WWDG1
SYSCFG
LPUART1
SPI6
I2C4
LPTIM2
LPTIM3
LPTIM4
LPTIM5
COMP12
VREF
RTCAPB
SAI4
DTS

◆ PLLClockSource

enum imt::base::hal::stm32h730::peripherals::RCC::PLLClockSource

strong

Enumeration for PLL Clock Source Configuration Chapter 8.7.10, RCC_PLLCSELR Bit 1:0 PLLSRC.

Enumerator
HSI	00: HSI selected as PLL clock (hsi_ck) (default after reset)
CSI	01: CSI selected as PLL clock (csi_ck)
HSE	10: HSE selected as PLL clock (hse_ck)
No	11: No clock send to DIVMx divider and PLLs

◆ PLLID

enum imt::base::hal::stm32h730::peripherals::RCC::PLLID

strong

Enumeration for PLL Configuration.

Enumerator
PLL1
PLL2
PLL3

◆ PllSaiDivR

enum imt::base::hal::stm32h730::peripherals::RCC::PllSaiDivR

strong

PLLSAI division factor for LCD_CLK.

Enumerator
Div2
Div4
Div8
Div16

◆ PLLState

enum imt::base::hal::stm32h730::peripherals::RCC::PLLState

strong

Enumeration for PLL Configuration.

Enumerator
None
Off
On

◆ RTCSource

enum imt::base::hal::stm32h730::peripherals::RCC::RTCSource

strong

Enumeration for possible RTC sources.

Enumerator
LSE
LSI
HSE

◆ SystemClockSource

enum imt::base::hal::stm32h730::peripherals::RCC::SystemClockSource

strong

Enumeration for system Clock Source Configuration Chapter 8.7.6, RCC_CFGR Bits 2:0 SW.

Enumerator
HSI	000: HSI selected as system clock (hsi_ck) (default after reset)
CSI	001:CSI selected as system clock (csi_ck)
HSE	010: HSE selected as system clock (hse_ck)
PLL1	011: PLL1 selected as system clock (pll1_p_ck)

◆ SystemClockType

enum imt::base::hal::stm32h730::peripherals::RCC::SystemClockType

strong

Enumeration for system clock type Configuration.

Enumerator
CPU
SYSCLK
HCLK
PCLK1
PCLK2
PCLK3
PCLK4

Member Function Documentation

◆ clearClockSecurityFailureFlag()

static void imt::base::hal::stm32h730::peripherals::RCC::clearClockSecurityFailureFlag ( )

static

Clears the CSS flag to not have an indefnite NMI irq.

◆ clearResetFlags()

static void imt::base::hal::stm32h730::peripherals::RCC::clearResetFlags ( )

static

Reset the reset flag of the RCC register.

◆ configureClock()

static bool imt::base::hal::stm32h730::peripherals::RCC::configureClock	(	const ClockConfigStruct &	clockConfig,
		const FLASH::Latency	flashLatency
	)

static

Initializes the CPU, AHB and APB busses clocks according to the specified parameters.

Parameters

clockConfig	specifies the parameters for Clock configuration
flashLatency	specifies the paramter for the flash latency

Returns

boolean - true: configuration successful

false: configuration failed

◆ configureClockMux()

static bool imt::base::hal::stm32h730::peripherals::RCC::configureClockMux	(	const ClockMux	clockMux,
		const ClockSource	source
	)

static

Initializes the CPU, AHB and APB busses clocks according to the specified parameters.

Parameters

clockMux	specifies the parameters for which mux to set
source	specifies the paramter for the mux source

Returns

boolean - true: configuration successful

false: configuration failed

◆ configureOscillator()

static bool imt::base::hal::stm32h730::peripherals::RCC::configureOscillator ( const OscillatorConfigStruct & oscConfig )

static

Initializes the RCC Oscillators according to the specified parameters.

Parameters

oscConfig specifies the parameters for RCC Oscillators

Returns

boolean - true: configuration successful

false: configuration failed

◆ configureRtc() [1/2]

static bool imt::base::hal::stm32h730::peripherals::RCC::configureRtc	(	const RTCSource	rtcSource,
		const bool	doEnable
	)

static

Initializes the CPU, AHB and APB busses clocks according to the specified parameters.

Parameters

rtcSource	used the specified clock as RTC source
doEnable	- true: enable RTC false: disable RTC

◆ configureRtc() [2/2]

static bool imt::base::hal::stm32h730::peripherals::RCC::configureRtc	(	const RTCSource	rtcSource,
		const bool	doEnable,
		uint8_t	divisorHSE
	)

static

◆ didWatchdogReset()

static bool imt::base::hal::stm32h730::peripherals::RCC::didWatchdogReset ( )

static

Checks if the reason for the reset was the independent watchdog.

◆ enableClockSecuritySystem()

static void imt::base::hal::stm32h730::peripherals::RCC::enableClockSecuritySystem ( )

static

Enables the clock security system which triggers an NMI interrupt when the HSE fails.

◆ enablePeripheralClock()

static void imt::base::hal::stm32h730::peripherals::RCC::enablePeripheralClock	(	const PeripheralModule	module,
		const bool	enabled
	)

static

Enables or disables the High Speed peripheral clock for the given module.

Parameters

module	specifies the peripheral to gates its clock.
enabled	true = ENABLE, false = DISABLE

◆ isLseReady()

static bool imt::base::hal::stm32h730::peripherals::RCC::isLseReady ( )

static

Returns if the LSE is running and ready.

◆ isLsiReady()

static bool imt::base::hal::stm32h730::peripherals::RCC::isLsiReady ( )

static

Returns if the LSI is running and ready.

◆ resetBDCR()

static void imt::base::hal::stm32h730::peripherals::RCC::resetBDCR ( void )

static

Resets the BDC Register, so new values can be written into it.

◆ resetPeripheralClock()

static void imt::base::hal::stm32h730::peripherals::RCC::resetPeripheralClock	(	const PeripheralModule	module,
		const bool	reset
	)

static

Enables or disables the reset flag for the given module.

Parameters

module	specifies the peripheral to gates its clock.
reset	true = ENABLE, false = DISABLE

The documentation for this class was generated from the following file:

D:/_Work/10/s/Imt.Base/Imt.Base.HAL.STM32H730/Peripherals/RCC.h

Classes

Public Types

Static Public Member Functions

Detailed Description

Member Enumeration Documentation

◆ AHBClockDivider

◆ APBxClockDivider

◆ ClockMux

◆ ClockSource

◆ I2CClockSource

◆ OscillatorState

◆ OscillatorType

◆ PeripheralModule

◆ PLLClockSource

◆ PLLID

◆ PllSaiDivR

◆ PLLState

◆ RTCSource

◆ SystemClockSource

◆ SystemClockType

Member Function Documentation

◆ clearClockSecurityFailureFlag()

◆ clearResetFlags()

◆ configureClock()

◆ configureClockMux()

◆ configureOscillator()

◆ configureRtc() [1/2]

◆ configureRtc() [2/2]

◆ didWatchdogReset()

◆ enableClockSecuritySystem()

◆ enablePeripheralClock()

◆ isLseReady()

◆ isLsiReady()

◆ resetBDCR()

◆ resetPeripheralClock()