RCC APB2 clock register (RCC_APB2ENR), chapter 8.7.46 Access: no wait state, word, half-word and byte access. More...

#include <Imt.Base.HAL.STM32H730/Registers/RCCRegisters.h>

Public Attributes
volatile uint32_t	TIM1EN: 1
	TIM1 enable. More...

volatile uint32_t	TIM8EN: 1
	TIM8 enable. More...

volatile	uint32_t: 2

volatile uint32_t	USART1EN: 1
	USART1 enable. More...

volatile uint32_t	USART6EN: 1
	USART6 enable. More...

volatile uint32_t	UART9EN: 1
	USART9 enable. More...

volatile uint32_t	USART10EN: 1
	USART10 enable. More...

volatile uint32_t	SPI1EN: 1
	SPI1 enable. More...

volatile uint32_t	SPI4EN: 1
	SPI4 enable. More...

volatile uint32_t	TIM15EN: 1
	TIM15 enable. More...

volatile uint32_t	TIM16EN: 1
	TIM16 enable. More...

volatile uint32_t	TIM17EN: 1
	TIM17 enable. More...

volatile uint32_t	SPI5EN: 1
	SPI5 enable. More...

volatile uint32_t	SAI1EN: 1
	SAI1 enable. More...

volatile uint32_t	DFSDM1EN: 1
	DFSDM1 module enable. More...

Detailed Description

RCC APB2 clock register (RCC_APB2ENR), chapter 8.7.46 Access: no wait state, word, half-word and byte access.

Member Data Documentation

◆ DFSDM1EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::DFSDM1EN

DFSDM1 module enable.

◆ SAI1EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::SAI1EN

SAI1 enable.

◆ SPI1EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::SPI1EN

SPI1 enable.

◆ SPI4EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::SPI4EN

SPI4 enable.

◆ SPI5EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::SPI5EN

SPI5 enable.

◆ TIM15EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::TIM15EN

TIM15 enable.

◆ TIM16EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::TIM16EN

TIM16 enable.

◆ TIM17EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::TIM17EN

TIM17 enable.

◆ TIM1EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::TIM1EN

TIM1 enable.

◆ TIM8EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::TIM8EN

TIM8 enable.

◆ UART9EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::UART9EN

USART9 enable.

◆ uint32_t

volatile imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::uint32_t

reserved

◆ USART10EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::USART10EN

USART10 enable.

◆ USART1EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::USART1EN

USART1 enable.

◆ USART6EN

volatile uint32_t imt::base::hal::stm32h730::registers::RCCRegisters::RCC_APB2ENR::USART6EN

USART6 enable.

The documentation for this struct was generated from the following file:

D:/_Work/10/s/Imt.Base/Imt.Base.HAL.STM32H730/Registers/RCCRegisters.h

Public Attributes