ADC3Registers.h

Go to the documentation of this file.

// (c) IMT - Information Management Technology AG, CH-9470 Buchs, www.imt.ch.
 
#ifndef STM32H730_ADC3REGISTERS_H
#define STM32H730_ADC3REGISTERS_H
 
#include <Imt.Base.Core.Platform/Platform.h>
#include <Imt.Base.HAL.STM32H730/SystemMemoryMap.h>
 
namespace imt {
namespace base {
namespace hal {
namespace stm32h730 {
namespace registers {
 
struct ADC3Registers {
    struct ADC_ISR {
        uint32_t volatile ADRDY : 1;  // ADC ready
        uint32_t volatile EOSMP : 1;  // End of sampling flag
        uint32_t volatile EOC   : 1;  // End of conversion flag
        uint32_t volatile EOS   : 1;  // End of regular sequence flag
        uint32_t volatile OVR   : 1;  // Overrun
        uint32_t volatile JEOC  : 1;  // Injected channel end of conversion.
        uint32_t volatile JEOS  : 1;  // Injected channel end of sequence flag
        uint32_t volatile AWD1  : 1;  // Analog watchdog 1 flag
        uint32_t volatile AWD2  : 1;  // Analog watchdog 2 flag
        uint32_t volatile AWD3  : 1;  // Analog watchdog 3 flag
        uint32_t volatile JQOVF : 1;  // Injected context queue overflow
        uint32_t volatile       : 21; // - reserved
    };
 
    struct ADC_IER {
        uint32_t volatile ADRDYIE : 1;  // ADC ready interrupt enable
        uint32_t volatile EOSMPIE : 1;  // End of sampling flag interrupt enable for regular conversions
        uint32_t volatile EOCIE   : 1;  // End of regular conversion interrupt enable
        uint32_t volatile EOSIE   : 1;  // End of regular sequence of conversions interrupt enable
        uint32_t volatile OVRIE   : 1;  // Overrun interrupt enable
        uint32_t volatile JEOCIE  : 1;  // End of injected conversion interrupt enable
        uint32_t volatile JEOSIE  : 1;  // End of injected sequence of conversions interrupt enable
        uint32_t volatile AWD1IE  : 1;  // Analog watchdog 1 interrupt enable
        uint32_t volatile AWD2IE  : 1;  // Analog watchdog 2 interrupt enable
        uint32_t volatile AWD3IE  : 1;  // Analog watchdog 3 interrupt enable
        uint32_t volatile JQOVFIE : 1;  // Injected context queue overflow interrupt enable
        uint32_t volatile         : 21; // - reserved
    };
 
    struct ADC_CR {
        uint32_t volatile ADEN     : 1;  // ADC enable control
        uint32_t volatile ADDIS    : 1;  // ADC disable command
        uint32_t volatile ADSTART  : 1;  // ADC start of regular conversion
        uint32_t volatile JADSTART : 1;  // ADC start of injected conversion
        uint32_t volatile ADSTP    : 1;  // ADC stop of regular conversion command
        uint32_t volatile JADSTP   : 1;  // ADC stop of injected conversion command
        uint32_t volatile          : 22; // - reserved
        uint32_t volatile ADVREGEN : 1;  // ADC voltage regulator enable
        uint32_t volatile DEEPPWD  : 1;  // Deep-power-down enable
        uint32_t volatile ADCALDIF : 1;  // Differential mode for calibration
        uint32_t volatile ADCAL    : 1;  // ADC calibration
    };
 
    struct ADC_CFGR {
        uint32_t volatile DMAEN    : 1; // Direct memory access enable
        uint32_t volatile DMACFG   : 1; // Direct memory access configuration
        uint32_t volatile DFSDMCFG : 1; // DFSDM mode configuration
        uint32_t volatile RES      : 2; // Data resolution
        uint32_t volatile EXTSEL   : 5; // External trigger selection for regular group
        uint32_t volatile EXTEN    : 2; // External trigger enable and polarity selection for regular channels
        uint32_t volatile OVRMOD   : 1; // Overrun mode
        uint32_t volatile CONT     : 1; // Single / Continuous conversion mode for regular conversions
        uint32_t volatile AUTDLY   : 1; // Delayed conversion mode
        uint32_t volatile ALIGN    : 1; // Data alignment
        uint32_t volatile DISCEN   : 1; // Discontinuous mode for regular channels
        uint32_t volatile DISCNUM  : 3; // Discontinuous mode channel count
        uint32_t volatile JDISCEN  : 1; // Discontinuous mode on injected channels
        uint32_t volatile JQM      : 1; // JSQR queue mode
        uint32_t volatile AWD1SGL  : 1; // Enable the watchdog 1 on a single channel or on all channels
        uint32_t volatile AWD1EN   : 1; // Analog watchdog 1 enable on regular channels
        uint32_t volatile JAWD1EN  : 1; // Analog watchdog 1 enable on injected channels
        uint32_t volatile JAUTO    : 1; // Automatic injected group conversion
        uint32_t volatile AWD1CH   : 5; // Analog watchdog 1 channel selection
        uint32_t volatile JQDIS    : 1; // Injected Queue disable
    };
 
    struct ADC_CFGR2 {
        uint32_t volatile ROVSE   : 1;  // Regular Oversampling Enable
        uint32_t volatile JOVSE   : 1;  // Injected Oversampling Enable
        uint32_t volatile OVSR    : 3;  // Oversampling ratio
        uint32_t volatile OVSS    : 4;  // Oversampling right shift
        uint32_t volatile TROVS   : 1;  // Triggered Regular Oversampling
        uint32_t volatile ROVSM   : 1;  // Regular Oversampling mode
        uint32_t volatile         : 14; // - reserved
        uint32_t volatile SWTRIG  : 1;  // Software trigger bit for sampling time control trigger mode
        uint32_t volatile BULB    : 1;  // Bulb sampling mode
        uint32_t volatile SMPTRIG : 1;  // Sampling time control trigger mode
        uint32_t volatile         : 4;  // - reserved
    };
 
    struct ADC_SMPR1 {
        uint32_t volatile SMP0    : 3; // Channel x sampling time selection (x = 0 to 9)
        uint32_t volatile SMP1    : 3; // Channel x sampling time selection (x = 0 to 9)
        uint32_t volatile SMP2    : 3; // Channel x sampling time selection (x = 0 to 9)
        uint32_t volatile SMP3    : 3; // Channel x sampling time selection (x = 0 to 9)
        uint32_t volatile SMP4    : 3; // Channel x sampling time selection (x = 0 to 9)
        uint32_t volatile SMP5    : 3; // Channel x sampling time selection (x = 0 to 9)
        uint32_t volatile SMP6    : 3; // Channel x sampling time selection (x = 0 to 9)
        uint32_t volatile SMP7    : 3; // Channel x sampling time selection (x = 0 to 9)
        uint32_t volatile SMP8    : 3; // Channel x sampling time selection (x = 0 to 9)
        uint32_t volatile SMP9    : 3; // Channel x sampling time selection (x = 0 to 9)
        uint32_t volatile         : 1; // - reserved
        uint32_t volatile SMPPLUS : 1; // Addition of one clock cycle to the sampling time
    };
 
    struct ADC_SMPR2 {
        uint32_t volatile SMP10 : 3; // Channel x sampling time selection (x = 10 to 19)
        uint32_t volatile SMP11 : 3; // Channel x sampling time selection (x = 10 to 19)
        uint32_t volatile SMP12 : 3; // Channel x sampling time selection (x = 10 to 19)
        uint32_t volatile SMP13 : 3; // Channel x sampling time selection (x = 10 to 19)
        uint32_t volatile SMP14 : 3; // Channel x sampling time selection (x = 10 to 19)
        uint32_t volatile SMP15 : 3; // Channel x sampling time selection (x = 10 to 19)
        uint32_t volatile SMP16 : 3; // Channel x sampling time selection (x = 10 to 19)
        uint32_t volatile SMP17 : 3; // Channel x sampling time selection (x = 10 to 19)
        uint32_t volatile SMP18 : 3; // Channel x sampling time selection (x = 10 to 19)
        uint32_t volatile       : 5; // - reserved
    };
 
    struct ADC_TR1 {
        uint32_t volatile LT1     : 12; // Analog watchdog 1 lower threshold
        uint32_t volatile AWDFILT : 3;  // Analog watchdog filtering parameter
        uint32_t volatile         : 1;  // - reserved
        uint32_t volatile HT1     : 12; // Analog watchdog 1 higher threshold
        uint32_t volatile         : 4;  // - reserved
    };
 
    struct ADC_TR2 {
        uint32_t volatile LT2 : 8; // Analog watchdog 2 lower threshold
        uint32_t volatile     : 8; // - reserved
        uint32_t volatile HT2 : 8; // Analog watchdog 2 higher threshold
        uint32_t volatile     : 8; // - reserved
    };
 
    struct ADC_TR3 {
        uint32_t volatile LT3 : 8; // Analog watchdog 3 lower threshold
        uint32_t volatile     : 8; // - reserved
        uint32_t volatile HT3 : 8; // Analog watchdog 3 higher threshold
        uint32_t volatile     : 8; // - reserved
    };
 
    struct ADC_SQR1 {
        uint32_t volatile L   : 4; // Regular channel sequence length
        uint32_t volatile     : 2; // - reserved
        uint32_t volatile SQ1 : 5; // 1st conversion in regular sequence
        uint32_t volatile     : 1; // - reserved
        uint32_t volatile SQ2 : 5; // 2nd conversion in regular sequence
        uint32_t volatile     : 1; // - reserved
        uint32_t volatile SQ3 : 5; // 3rd conversion in regular sequence
        uint32_t volatile     : 1; // - reserved
        uint32_t volatile SQ4 : 5; // 4th conversion in regular sequence
        uint32_t volatile     : 3; // - reserved
    };
 
    struct ADC_SQR2 {
        uint32_t volatile SQ5 : 5; // 5th conversion in regular sequence
        uint32_t volatile     : 1; // - reserved
        uint32_t volatile SQ6 : 5; // 6th conversion in regular sequence
        uint32_t volatile     : 1; // - reserved
        uint32_t volatile SQ7 : 5; // 7th conversion in regular sequence
        uint32_t volatile     : 1; // - reserved
        uint32_t volatile SQ8 : 5; // 8th conversion in regular sequence
        uint32_t volatile     : 1; // - reserved
        uint32_t volatile SQ9 : 5; // 9th conversion in regular sequence
        uint32_t volatile     : 3; // - reserved
    };
 
    struct ADC_SQR3 {
        uint32_t volatile SQ10 : 5; // 10th conversion in regular sequence
        uint32_t volatile      : 1; // - reserved
        uint32_t volatile SQ11 : 5; // 11th conversion in regular sequence
        uint32_t volatile      : 1; // - reserved
        uint32_t volatile SQ12 : 5; // 12th conversion in regular sequence
        uint32_t volatile      : 1; // - reserved
        uint32_t volatile SQ13 : 5; // 13th conversion in regular sequence
        uint32_t volatile      : 1; // - reserved
        uint32_t volatile SQ14 : 5; // 14th conversion in regular sequence
        uint32_t volatile      : 3; // - reserved
    };
 
    struct ADC_SQR4 {
        uint32_t volatile SQ15 : 5;  // 15th conversion in regular sequence
        uint32_t volatile      : 1;  // - reserved
        uint32_t volatile SQ16 : 5;  // 16th conversion in regular sequence
        uint32_t volatile      : 21; // - reserved
    };
 
    struct ADC_DR {
        uint32_t volatile RDATA : 16; // Regular data converted
        uint32_t volatile       : 16; // - reserved
    };
 
    struct ADC_JSQR {
        uint32_t volatile JL      : 2; // Injected channel sequence length
        uint32_t volatile JEXTSEL : 5; // External trigger selection for injected group
        uint32_t volatile JEXTEN  : 2; // External trigger enable and polarity selection for injected channels
        uint32_t volatile JSQ1    : 5; // 1st conversion in the injected sequence
        uint32_t volatile         : 1; // - reserved
        uint32_t volatile JSQ2    : 5; // 2nd conversion in the injected sequence
        uint32_t volatile         : 1; // - reserved
        uint32_t volatile JSQ3    : 5; // 3rd conversion in the injected sequence
        uint32_t volatile         : 1; // - reserved
        uint32_t volatile JSQ4    : 5; // 4th conversion in the injected sequence
    };
 
    struct ADC_OFRy {
        uint32_t volatile OFFSETy    : 12; // 1Data offset y for the channel programmed into bits OFFSETy_CH[4:0]
        uint32_t volatile            : 12; // - reserved
        uint32_t volatile OFFSETPOS  : 1;  // Positive offset
        uint32_t volatile SATEN      : 1;  // Saturation enable
        uint32_t volatile OFFSETy_CH : 5;  // Channel selection for the data offset y
        uint32_t volatile OFFSETy_EN : 1;  // Offset y enable
    };
 
    struct ADC_JDRy {
        uint32_t volatile JDATA : 16; // Injected data
        uint32_t volatile       : 16; // - reserved
    };
 
    struct ADC_AWDxCR {
        uint32_t volatile AWDxCH : 19; // Analog watchdog x channel selection
        uint32_t volatile        : 13; // - reserved
    };
 
    struct ADC_DIFSEL {
        uint32_t volatile DIFSEL : 19; // Differential mode for channels 19 to 0
        uint32_t volatile        : 13; // - reserved
    };
 
    struct ADC_CALFACT {
        uint32_t volatile CALFACT_S : 7; // Calibration Factors In Single-Ended mode
        uint32_t volatile           : 9; // - reserved
        uint32_t volatile CALFACT_D : 7; // Calibration Factors In differential mode
        uint32_t volatile           : 9; // - reserved
    };
 
    static ADC3Registers& getInstance(ADCModuleAddress const module) {
        return *reinterpret_cast<ADC3Registers*>(module);
    }
 
    // Registers
    volatile ADC_ISR ISR;     // Offset 0x00
    volatile ADC_IER IER;     // Offset 0x04
    volatile ADC_CR CR;       // Offset 0x08
    volatile ADC_CFGR CFGR;   // Offset 0x0C
    volatile ADC_CFGR2 CFGR2; // Offset 0x10
    volatile ADC_SMPR1 SMPR1; // Offset 0x14
    volatile ADC_SMPR2 SMPR2; // Offset 0x18
    uint32_t volatile _reserved0;
    volatile ADC_TR1 TR1; // Offset 0x20
    volatile ADC_TR2 TR2; // Offset 0x24
    volatile ADC_TR3 TR3; // Offset 0x28
    uint32_t volatile _reserved1;
    volatile ADC_SQR1 SQR1; // Offset 0x30
    volatile ADC_SQR2 SQR2; // Offset 0x34
    volatile ADC_SQR3 SQR3; // Offset 0x38
    volatile ADC_SQR4 SQR4; // Offset 0x3C
    volatile ADC_DR DR;     // Offset 0x40
    uint32_t volatile _reserved2[2U];
    volatile ADC_JSQR JSQR; // Offset 0x4C
    uint32_t volatile _reserved3[4U];
    ADC_OFRy volatile OFR1; // Offset 0x60
    ADC_OFRy volatile OFR2; // Offset 0x64
    ADC_OFRy volatile OFR3; // Offset 0x68
    ADC_OFRy volatile OFR4; // Offset 0x6C
    uint32_t volatile _reserved4[4U];
    ADC_JDRy volatile JDR1; // Offset 0x80
    ADC_JDRy volatile JDR2; // Offset 0x84
    ADC_JDRy volatile JDR3; // Offset 0x88
    ADC_JDRy volatile JDR4; // Offset 0x8C
    uint32_t volatile _reserved5[4U];
    ADC_AWDxCR volatile AWD2CR; // Offset 0xA0
    ADC_AWDxCR volatile AWD3CR; // Offset 0xA4
    uint32_t volatile _reserved6[2U];
    volatile ADC_DIFSEL DIFSEL;   // Offset 0xB0
    volatile ADC_CALFACT CALFACT; // Offset 0xB4
 
private:
 
    ADC3Registers();
 
    ADC3Registers(ADC3Registers const& other);
 
    ADC3Registers& operator=(ADC3Registers const& other);
};
 
} // namespace registers
} // namespace stm32h730
} // namespace hal
} // namespace base
} // namespace imt
 
#endif // STM32H730_ADC3REGISTERS_H