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Core_CortexM0.h
Go to the documentation of this file.
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// (c) IMT - Information Management Technology AG, CH-9470 Buchs, www.imt.ch.
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#ifndef CORE_CORTEXM0_H
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#define CORE_CORTEXM0_H
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#include <
Imt.Base.Core.Platform/Platform.h
>
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#include <
Imt.Base.HAL.STM32F030/SystemMemoryMap.h
>
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// Reference: Cortex-M0 Devices Generic User Guide DUI0497A Table 4-10
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// System Control Block (SCB) register structure
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typedef
struct
{
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// Offset: 0x00 CPU ID Base Register
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uint32_t
volatile
CPUID
;
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// Offset: 0x04 Interrupt Control State Register
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uint32_t
volatile
ICSR
;
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// Offset: 0x08 Vector Table Offset Register
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uint32_t
volatile
VTOR
;
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// Offset: 0x0C Application Interrupt / Reset Control Register
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uint32_t
volatile
AIRCR
;
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// Offset: 0x10 System Control Register
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uint32_t
volatile
SCR
;
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// Offset: 0x14 Configuration Control Register
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uint32_t
volatile
CCR
;
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// Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15)
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uint8_t
volatile
SHPR[3];
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}
SCB_Type
;
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// SCB configuration struct
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#define SCB ((SCB_Type*)SCB_BASE)
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// Bit definition for SCB_ICSR register
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// Active ISR number field
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#define SCB_ICSR_VECTACTIVE ((uint32_t)0x0000001F)
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// Pending ISR number field
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#define SCB_ICSR_VECTPENDING ((uint32_t)0x0003F000)
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// Interrupt pending flag
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#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000)
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// Clear pending SysTick bit
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#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000)
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// Set pending SysTick bit
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#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000)
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// Clear pending pendSV bit
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#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000)
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// Set pending pendSV bit
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#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000)
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// Set pending NMI bit
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#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000)
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// Bit definition for SCB_SCR register
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// Sleep deep bit
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#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04)
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// SCB Application Interrupt and Reset Control Register Definitions
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// SCB AIRCR: VECTKEY Position
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#define SCB_AIRCR_VECTKEY_Pos 16
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// SCB AIRCR: VECTKEY Mask
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#define SCB_AIRCR_VECTKEY_Mask (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
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// SCB AIRCR: SYSRESETREQ Position
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#define SCB_AIRCR_SYSRESETREQ_Pos 2U
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// SCB AIRCR: SYSRESETREQ Mask
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#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
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#endif
// CORE_CORTEXM0_H
SystemMemoryMap.h
Platform.h
uint32_t
unsigned __int32 uint32_t
Definition
stdint.h:64
uint8_t
unsigned __int8 uint8_t
Definition
stdint.h:62
SCB_Type
Definition
Core_CortexM0.h:11
SCB_Type::CCR
uint32_t volatile CCR
Definition
Core_CortexM0.h:23
SCB_Type::AIRCR
uint32_t volatile AIRCR
Definition
Core_CortexM0.h:19
SCB_Type::SCR
uint32_t volatile SCR
Definition
Core_CortexM0.h:21
SCB_Type::CPUID
uint32_t volatile CPUID
Definition
Core_CortexM0.h:13
SCB_Type::VTOR
uint32_t volatile VTOR
Definition
Core_CortexM0.h:17
SCB_Type::ICSR
uint32_t volatile ICSR
Definition
Core_CortexM0.h:15
Imt.Base
Imt.Base.HAL.STM32F030
Core_CortexM0.h
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