DMAMUX.h

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// (c) IMT - Information Management Technology AG, CH-9470 Buchs, www.imt.ch.
 
#ifndef STM32H730_DMAMUX_H
#define STM32H730_DMAMUX_H
 
#include <Imt.Base.Core.Platform/Platform.h>
#include <Imt.Base.HAL.STM32H730/SystemMemoryMap.h>
 
namespace imt {
namespace base {
namespace hal {
namespace stm32h730 {
namespace peripherals {
 
class DMAMUX {
public:
 
    enum class MultiplexerInput {
        dmamux1_req_gen0 = 1U,
        dmamux1_req_gen1 = 2U,
        dmamux1_req_gen2 = 3U,
        dmamux1_req_gen3 = 4U,
        dmamux1_req_gen4 = 5U,
        dmamux1_req_gen5 = 6U,
        dmamux1_req_gen6 = 7U,
        dmamux1_req_gen7 = 8U,
        adc1_dma = 9U,
        adc2_dma = 10U,
        TIM1_CH1 = 11U,
        TIM1_CH2 = 12U,
        TIM1_CH3 = 13U,
        TIM1_CH4 = 14U,
        TIM1_UP = 15U,
        TIM1_TRIG = 16U,
        TIM1_COM = 17U,
        TIM2_CH1 = 18U,
        TIM2_CH2 = 19U,
        TIM2_CH3 = 20U,
        TIM2_CH4 = 21U,
        TIM2_UP = 22U,
        TIM3_CH1 = 23U,
        TIM3_CH2 = 24U,
        TIM3_CH3 = 25U,
        TIM3_CH4 = 26U,
        TIM3_UP = 27U,
        TIM3_TRIG = 28U,
        TIM4_CH1 = 29U,
        TIM4_CH2 = 30U,
        TIM4_CH3 = 31U,
        TIM4_UP = 32U,
        i2c1_rx_dma = 33U,
        i2c1_tx_dma = 34U,
        i2c2_rx_dma = 35U,
        i2c2_tx_dma = 36U,
        spi1_rx_dma = 37U,
        spi1_tx_dma = 38U,
        spi2_rx_dma = 39U,
        spi2_tx_dma = 40U,
        usart1_rx_dma = 41U,
        usart1_tx_dma = 42U,
        usart2_rx_dma = 43U,
        usart2_tx_dma = 44U,
        usart3_rx_dma = 45U,
        usart3_tx_dma = 46U,
        TIM8_CH1 = 47U,
        TIM8_CH2 = 48U,
        TIM8_CH3 = 49U,
        TIM8_CH4 = 50U,
        TIM8_UP = 51U,
        TIM8_TRIG = 52U,
        TIM8_COM = 53U,
        TIM5_CH1 = 55U,
        TIM5_CH2 = 56U,
        TIM5_CH3 = 57U,
        TIM5_CH4 = 58U,
        TIM5_UP = 59U,
        TIM5_TRIG = 60U,
        spi3_rx_dma = 61U,
        spi3_tx_dma = 62U,
        uart4_rx_dma = 63U,
        uart4_tx_dma = 64U,
        uart5_rx_dma = 65U,
        uart5_tx_dma = 66U,
        dac_ch1_dma = 67U,
        dac_ch2_dma = 68U,
        TIM6_UP = 69U,
        TIM7_UP = 70U,
        usart6_rx_dma = 71U,
        usart6_tx_dma = 72U,
        i2c3_rx_dma = 73U,
        i2c3_tx_dma = 74U,
        dcmi_dma = 75U,
        cryp_in_dma = 76U,
        cryp_out_dma = 77U,
        hash_in_dma = 78U,
        uart7_rx_dma = 79U,
        uart7_tx_dma = 80U,
        uart8_rx_dma = 81U,
        uart8_tx_dma = 82U,
        spi4_rx_dma = 83U,
        spi4_tx_dma = 84U,
        spi5_rx_dma = 85U,
        spi5_tx_dma = 86U,
        sai1a_dma = 87U,
        sai1b_dma = 88U,
        swpmi_rx_dma = 91U,
        swpmi_tx_dma = 92U,
        spdifrx_dat_dma = 93U,
        spdifrx_ctrl_dma = 94U,
        dfsdm1_dma0 = 101U,
        dfsdm1_dma1 = 102U,
        dfsdm1_dma2 = 103U,
        dfsdm1_dma3 = 104U,
        TIM15_CH1 = 105U,
        TIM15_UP = 106U,
        TIM15_TRIG = 107U,
        TIM15_COM = 108U,
        TIM16_CH1 = 109U,
        TIM16_UP = 110U,
        TIM17_CH1 = 111U,
        TIM17_UP = 112U,
        adc3_dma = 115U,
        uart9_rx_dma = 116U,
        uart9_tx_dma = 117U,
        uart10_rx_dma = 118U,
        uart10_tx_dma = 119U,
        FMAC_RD = 120U,
        FMAC_WR = 121U,
        CORDIC_RD = 122U,
        CORDIC_WR = 123U,
        i2c5_rx_dma = 124U,
        i2c5_tx_dma = 125U,
        TIM23_CH1 = 126U,
        TIM23_CH2 = 127U,
        TIM23_CH3 = 128U,
        TIM23_CH4 = 129U,
        TIM23_UP = 130U,
        TIM23_TRIG = 131U,
        TIM24_CH1 = 132U,
        TIM24_CH2 = 133U,
        TIM24_CH3 = 134U,
        TIM24_CH4 = 135U,
        TIM24_UP = 136U,
        TIM24_TRIG = 137U
    };
 
    enum class TriggerInput {
        dmamux1_evt0 = 0U,
        dmamux1_evt1 = 1U,
        dmamux1_evt2 = 2U,
        lptim1_out = 3U,
        lptim2_out = 4U,
        lptim3_out = 5U,
        extit0 = 6U,
        TIM12_TRGO = 7U
    };
 
    enum class SyncInput {
        dmamux1_evt0 = 0U,
        dmamux1_evt1 = 1U,
        dmamux1_evt2 = 2U,
        lptim1_out = 3U,
        lptim2_out = 4U,
        lptim3_out = 5U,
        extit0 = 6U,
        TIM12_TRGO = 7U
    };
 
    static bool init(DMAStreamModuleAddress const module, MultiplexerInput const resource);
 
    static void deInit(DMAStreamModuleAddress const module);
 
private:
 
    DMAMUX();
 
    DMAMUX(const DMAMUX& other);
 
    DMAMUX& operator=(const DMAMUX& other);
};
 
} // namespace peripherals
} // namespace stm32h730
} // namespace hal
} // namespace base
} // namespace imt
 
#endif // STM32H730_DMAMUX_H