DMAMUXRegisters.h

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// (c) IMT - Information Management Technology AG, CH-9470 Buchs, www.imt.ch.
 
#ifndef STM32H730_DMAMUXREGISTERS_H
#define STM32H730_DMAMUXREGISTERS_H
 
#include <Imt.Base.Core.Platform/Platform.h>
#include <Imt.Base.HAL.STM32H730/SystemMemoryMap.h>
 
namespace imt {
namespace base {
namespace hal {
namespace stm32h730 {
namespace registers {
 
struct DMAMUXRegisters {
    union DMAMUX_CxCR {
        struct DMAMUX1_CxCR {
            uint32_t volatile DMAREQ_ID : 7; // DMA request identification
            uint32_t volatile           : 1; // - reserved
            uint32_t volatile SOIE      : 1; // SSynchronization overrun interrupt enable
            uint32_t volatile EGE       : 1; // Event generation enable
            uint32_t volatile           : 6; // - reserved
            uint32_t volatile SE        : 1; // Synchronization enable
            uint32_t volatile SPOL      : 2; // Synchronization polarity
            uint32_t volatile NBREQ     : 5; // Number of DMA requests minus 1 to forward
            uint32_t volatile SYNC_ID   : 3; // Synchronization identification
            uint32_t volatile           : 5; // - reserved
        };
 
        struct DMAMUX2_CxCR {
            uint32_t volatile DMAREQ_ID : 5; // DMA request identification
            uint32_t volatile           : 3; // - reserved
            uint32_t volatile SOIE      : 1; // SSynchronization overrun interrupt enable
            uint32_t volatile EGE       : 1; // Event generation enable
            uint32_t volatile           : 6; // - reserved
            uint32_t volatile SE        : 1; // Synchronization enable
            uint32_t volatile SPOL      : 2; // Synchronization polarity
            uint32_t volatile NBREQ     : 5; // Number of DMA requests minus 1 to forward
            uint32_t volatile SYNC_ID   : 5; // Synchronization identification
            uint32_t volatile           : 3; // - reserved
        };
 
        DMAMUX1_CxCR volatile DMAMUX1; 
        DMAMUX2_CxCR volatile DMAMUX2; 
    };
 
    union DMAMUX_CSR {
        struct DMAMUX1_CSR {
            uint32_t volatile SOF0  : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF1  : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF2  : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF3  : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF4  : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF5  : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF6  : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF7  : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF8  : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF9  : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF10 : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF11 : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF12 : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF13 : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF14 : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF15 : 1;  // Synchronization overrun event flag
            uint32_t volatile       : 16; // - reserved
        };
 
        struct DMAMUX2_CSR {
            uint32_t volatile SOF0 : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF1 : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF2 : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF3 : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF4 : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF5 : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF6 : 1;  // Synchronization overrun event flag
            uint32_t volatile SOF7 : 1;  // Synchronization overrun event flag
            uint32_t volatile      : 24; // - reserved
        };
 
        volatile DMAMUX1_CSR DMAMUX1; 
        volatile DMAMUX2_CSR DMAMUX2; 
    };
 
    union DMAMUX_CFR {
        struct DMAMUX1_CFR {
            uint32_t volatile CSOF0  : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF1  : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF2  : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF3  : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF4  : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF5  : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF6  : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF7  : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF8  : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF9  : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF10 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF11 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF12 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF13 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF14 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF15 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile        : 16; // - reserved
        };
 
        struct DMAMUX2_CFR {
            uint32_t volatile CSOF0 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF1 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF2 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF3 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF4 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF5 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF6 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile CSOF7 : 1;  // Clear Synchronization overrun event flag
            uint32_t volatile       : 24; // - reserved
        };
 
        volatile DMAMUX1_CFR DMAMUX1; 
        volatile DMAMUX2_CFR DMAMUX2; 
    };
 
    union DMAMUX_RGxCR {
        struct DMAMUX1_RGxCR {
            uint32_t volatile SIG_ID : 3; // Signal identification
            uint32_t volatile        : 5; // - reserved
            uint32_t volatile OIE    : 1; // Trigger overrun interrupt enable
            uint32_t volatile        : 7; // - reserved
            uint32_t volatile GE     : 1; // DMA request generator channel x enable
            uint32_t volatile GPOL   : 2; // DMA request generator trigger polarity
            uint32_t volatile GNBREQ : 5; // Number of DMA requests to be generated (minus 1)
            uint32_t volatile        : 8; // - reserved
        };
 
        struct DMAMUX2_RGxCR {
            uint32_t volatile SIG_ID : 5; // Signal identification
            uint32_t volatile        : 3; // - reserved
            uint32_t volatile OIE    : 1; // Trigger overrun interrupt enable
            uint32_t volatile        : 7; // - reserved
            uint32_t volatile GE     : 1; // DMA request generator channel x enable
            uint32_t volatile GPOL   : 2; // DMA request generator trigger polarity
            uint32_t volatile GNBREQ : 5; // Number of DMA requests to be generated (minus 1)
            uint32_t volatile        : 8; // - reserved
        };
 
        DMAMUX1_RGxCR volatile DMAMUX1; 
        DMAMUX2_RGxCR volatile DMAMUX2; 
    };
 
    union DMAMUX_RGSR {
        struct DMAMUX1_RGSR {
            uint32_t volatile OF0 : 1;  // Trigger overrun event flag
            uint32_t volatile OF1 : 1;  // Trigger overrun event flag
            uint32_t volatile OF2 : 1;  // Trigger overrun event flag
            uint32_t volatile OF3 : 1;  // Trigger overrun event flag
            uint32_t volatile OF4 : 1;  // Trigger overrun event flag
            uint32_t volatile OF5 : 1;  // Trigger overrun event flag
            uint32_t volatile OF6 : 1;  // Trigger overrun event flag
            uint32_t volatile OF7 : 1;  // Trigger overrun event flag
            uint32_t volatile     : 24; // - reserved
        };
 
        struct DMAMUX2_RGSR {
            uint32_t volatile OF0 : 1;  // Trigger overrun event flag
            uint32_t volatile OF1 : 1;  // Trigger overrun event flag
            uint32_t volatile OF2 : 1;  // Trigger overrun event flag
            uint32_t volatile OF3 : 1;  // Trigger overrun event flag
            uint32_t volatile OF4 : 1;  // Trigger overrun event flag
            uint32_t volatile OF5 : 1;  // Trigger overrun event flag
            uint32_t volatile OF6 : 1;  // Trigger overrun event flag
            uint32_t volatile OF7 : 1;  // Trigger overrun event flag
            uint32_t volatile     : 24; // - reserved
        };
 
        volatile DMAMUX1_RGSR DMAMUX1; 
        volatile DMAMUX2_RGSR DMAMUX2; 
    };
 
    union DMAMUX_RGCFR {
        struct DMAMUX1_RGCFR {
            uint32_t volatile COF0 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF1 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF2 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF3 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF4 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF5 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF6 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF7 : 1;  // Clear trigger overrun event flag
            uint32_t volatile      : 24; // - reserved
        };
 
        struct DMAMUX2_RGCFR {
            uint32_t volatile COF0 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF1 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF2 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF3 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF4 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF5 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF6 : 1;  // Clear trigger overrun event flag
            uint32_t volatile COF7 : 1;  // Clear trigger overrun event flag
            uint32_t volatile      : 24; // - reserved
        };
 
        volatile DMAMUX1_RGCFR DMAMUX1; 
        volatile DMAMUX2_RGCFR DMAMUX2; 
    };
 
    static DMAMUXRegisters& getInstance(DMAMUXModuleAddress const module) {
        return *reinterpret_cast<DMAMUXRegisters*>(module);
    }
 
    // Registers
    DMAMUX_CxCR volatile C0CR;        // Offset 0x00
    DMAMUX_CxCR volatile C1CR;        // Offset 0x04
    DMAMUX_CxCR volatile C2CR;        // Offset 0x08
    DMAMUX_CxCR volatile C3CR;        // Offset 0x0C
    DMAMUX_CxCR volatile C4CR;        // Offset 0x10
    DMAMUX_CxCR volatile C5CR;        // Offset 0x14
    DMAMUX_CxCR volatile C6CR;        // Offset 0x18
    DMAMUX_CxCR volatile C7CR;        // Offset 0x1C
    DMAMUX_CxCR volatile C8CR;        // Offset 0x20
    DMAMUX_CxCR volatile C9CR;        // Offset 0x24
    DMAMUX_CxCR volatile C10CR;       // Offset 0x28
    DMAMUX_CxCR volatile C11CR;       // Offset 0x2C
    DMAMUX_CxCR volatile C12CR;       // Offset 0x30
    DMAMUX_CxCR volatile C13CR;       // Offset 0x34
    DMAMUX_CxCR volatile C14CR;       // Offset 0x38
    DMAMUX_CxCR volatile C15CR;       // Offset 0x3C
    uint32_t volatile _reserved0[16]; // Offset 0x40
    volatile DMAMUX_CSR CSR;          // Offset 0x80
    volatile DMAMUX_CFR CFR;          // Offset 0x84
    uint32_t volatile _reserved1[30]; // Offset 0x88
    DMAMUX_RGxCR volatile RG0CR;      // Offset 0x100
    DMAMUX_RGxCR volatile RG1CR;      // Offset 0x104
    DMAMUX_RGxCR volatile RG2CR;      // Offset 0x108
    DMAMUX_RGxCR volatile RG3CR;      // Offset 0x10C
    DMAMUX_RGxCR volatile RG4CR;      // Offset 0x110
    DMAMUX_RGxCR volatile RG5CR;      // Offset 0x114
    DMAMUX_RGxCR volatile RG6CR;      // Offset 0x118
    DMAMUX_RGxCR volatile RG7CR;      // Offset 0x11C
    uint32_t volatile _reserved2[8];  // Offset 0x120
    volatile DMAMUX_RGSR RGSR;        // Offset 0x140
    volatile DMAMUX_RGCFR RGCFR;      // Offset 0x144
 
private:
 
    DMAMUXRegisters();
 
    DMAMUXRegisters(DMAMUXRegisters const& other);
 
    DMAMUXRegisters& operator=(DMAMUXRegisters const& other);
};
 
} // namespace registers
} // namespace stm32h730
} // namespace hal
} // namespace base
} // namespace imt
 
#endif // STM32H730_DMAMUXREGISTERS_H