OSPI.h

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// (c) IMT - Information Management Technology AG, CH-9470 Buchs, www.imt.ch.
 
#ifndef STM32H730_OSPI_H
#define STM32H730_OSPI_H
 
#include <Imt.Base.Core.Platform/Platform.h>
#include <Imt.Base.HAL.STM32H730/SystemMemoryMap.h>
 
namespace imt {
namespace base {
namespace hal {
namespace stm32h730 {
namespace peripherals {
 
class OSPI {
public:
 
    enum class SampleShift {
        NoShift,
        HalfCycleShift
    };
 
    enum class ChipSelectHighTime {
        Cycle1,  
        Cycle2,  
        Cycle3,  
        Cycle4,  
        Cycle5,  
        Cycle6,  
        Cycle7,  
        Cycle8,  
        Cycle9,  
        Cycle10, 
        Cycle11, 
        Cycle12, 
        Cycle13, 
        Cycle14, 
        Cycle15, 
        Cycle16, 
        Cycle17, 
        Cycle18, 
        Cycle19, 
        Cycle20, 
        Cycle21, 
        Cycle22, 
        Cycle23, 
        Cycle24, 
        Cycle25, 
        Cycle26, 
        Cycle27, 
        Cycle28, 
        Cycle29, 
        Cycle30, 
        Cycle31, 
        Cycle32, 
        Cycle33, 
        Cycle34, 
        Cycle35, 
        Cycle36, 
        Cycle37, 
        Cycle38, 
        Cycle39, 
        Cycle40, 
        Cycle41, 
        Cycle42, 
        Cycle43, 
        Cycle44, 
        Cycle45, 
        Cycle46, 
        Cycle47, 
        Cycle48, 
        Cycle49, 
        Cycle50, 
        Cycle51, 
        Cycle52, 
        Cycle53, 
        Cycle54, 
        Cycle55, 
        Cycle56, 
        Cycle57, 
        Cycle58, 
        Cycle59, 
        Cycle60, 
        Cycle61, 
        Cycle62, 
        Cycle63, 
        Cycle64  
    };
 
    enum class Mode {
        Mode0, 
        Mode3  
    };
 
    enum class FlashMemorySelection {
        Flash1,
        Flash2
    };
 
    enum class DualQuadMode {
        disabled,
        enabled
    };
 
    enum class MemoryType {
        Micron = 0U,
        Macronix = 1U,
        Standard = 2U,
        MacronixRam = 3U,
        HyperBusSingle = 4U,
        HyperBusRegister = 5U
    };
 
    enum class FreeRunningClock {
        notFreeRunning,
        FreeRunning
    };
 
    enum class WrapSize {
        notSupported = 0U,
        Bytes16 = 2U,
        Bytes32 = 3U,
        Bytes64 = 4U,
        Bytes128 = 5U
    };
 
    struct InitStruct {
        uint32_t clockPrescaler;               
        uint32_t fifoThreshold;                
        SampleShift sampleShift;               
        uint32_t flashSize;                    
        ChipSelectHighTime chipSelectHighTime; 
        Mode mode;                             
        FlashMemorySelection flashId;          
        DualQuadMode dualQuad;                 
        MemoryType MemType;                    
        FreeRunningClock freeRunningClock;     
        WrapSize wrapSize;                     
    };
 
    enum class ByteSize {
        Bit8,
        Bit16,
        Bit24,
        Bit32
    };
 
    enum class DataLines {
        None,
        Line1,
        Line2,
        Line4,
        Line8
    };
 
    enum class DDR_SIOO_Mode {
        InstructionEveryCommand,
        InstructionOnly1stCommand
    };
 
    struct CommandInitStruct {
        uint32_t instruction;        
        ByteSize instructionSize;    
        uint32_t address;            
        uint32_t alternateBytes;     
        ByteSize addressSize;        
        ByteSize alternateByteSize;  
        uint32_t dummyCycle;         
        DataLines instructionMode;   
        DataLines addressMode;       
        DataLines alternateByteMode; 
        DataLines dataMode;          
        uint32_t numberData;         
        DDR_SIOO_Mode siooMode;      
    };
 
    enum class MatchMode {
        And,
        Or
    };
 
    enum class AutomaticStop {
        Disable,
        Enable
    };
 
    struct AutoPollingInitStructure {
        uint32_t match;              
        uint32_t mask;               
        uint32_t interval;           
        uint32_t statusByteSize;     
        MatchMode matchMode;         
        AutomaticStop automaticStop; 
    };
 
    enum class FunctionalMode {
        IndirectWrite,
        IndirectRead,
        AutoPolling,
        MemoryMapped
    };
 
    enum class TimeOutActivation {
        Disable,
        Enable
    };
 
    struct MemoryMapInitStructure {
        uint32_t timeOutPeriod;              
        TimeOutActivation timeOutActivation; 
    };
 
    static bool init(OCTOSPIModuleAddress module, InitStruct const& initStruct);
 
    static void deInit();
 
    static bool commandBlocking(OCTOSPIModuleAddress module, CommandInitStruct const& initStruct, uint32_t const timeout);
 
    static bool command(OCTOSPIModuleAddress module, CommandInitStruct const& initStruct, uint32_t const timeout);
 
    static void configureAutoPollingModeBlocking(OCTOSPIModuleAddress module, CommandInitStruct& initStruct, AutoPollingInitStructure const& apInitStruct, uint32_t const timeout);
 
    static void configureAutoPollingMode(OCTOSPIModuleAddress module, CommandInitStruct& initStruct, AutoPollingInitStructure const& apInitStruct, uint32_t const timeout);
 
    static void receiveBlocking(OCTOSPIModuleAddress module, uint8_t* pData, uint32_t const timeout);
 
    static void receive(OCTOSPIModuleAddress module, uint8_t* const pData);
 
    static void transmitBlocking(OCTOSPIModuleAddress module, uint8_t const* pData, uint32_t const timeout);
 
    static void transmit(OCTOSPIModuleAddress module, uint8_t const* const pData);
 
    static void configureMemoryMappedMode(OCTOSPIModuleAddress module, CommandInitStruct const& cmdInitStruct, MemoryMapInitStructure const& mmInitStruct);
 
    static bool isBusy(OCTOSPIModuleAddress module);
 
    static void cancel(OCTOSPIModuleAddress module);
 
    static void onFTInterrupt(OCTOSPIModuleAddress module);
 
    static void onTCInterrupt(OCTOSPIModuleAddress module);
 
    static void onSMInterrupt(OCTOSPIModuleAddress module);
 
    static void onTEInterrupt(OCTOSPIModuleAddress module);
 
    static void onTOInterrupt(OCTOSPIModuleAddress module);
 
    static void readData(OCTOSPIModuleAddress module, CommandInitStruct const& cmdInitStruct, uint8_t* pData, uint32_t const maxlen);
 
    static void writeData(OCTOSPIModuleAddress module, CommandInitStruct const& cmdInitStruct, uint32_t const* pData, uint32_t const timeout);
 
private:
 
    OSPI();
 
    OSPI(const OSPI& other);
 
    OSPI& operator=(const OSPI& other);
 
    static bool checkCommandInitStructParameters(CommandInitStruct const& initStruct);
 
    static void configure(OCTOSPIModuleAddress module, CommandInitStruct const& initStruct, FunctionalMode const functionalMode);
 
    static uint32_t const FIFIO_BUFFER_SIZE = 32U;
 
    static uint8_t s_txBuffer[FIFIO_BUFFER_SIZE];
    static uint8_t s_bytesToTransmit;
    static uint8_t s_transmitedBytes;
    static uint8_t* s_rxBuffer;
    static uint32_t s_bytesToReceive;
    static uint8_t s_receivedBytes;
};
 
} // namespace peripherals
} // namespace stm32h730
} // namespace hal
} // namespace base
} // namespace imt
 
#endif // #define STM32H730_OSPI_H