Imt.Base C++ API V4.1.1.0
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imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR Struct Reference

RCC APB2 peripheral clock enable in low-power mode register (RCC_APB2LPENR), chapter 5.3.19 Access: no wait state, word, half-word and byte access. More...

#include <Imt.Base.HAL.STM32F767/Registers/RCCRegisters.h>

Public Attributes

uint32_t volatile TIM1LPEN: 1
 TIM1 clock enable during Sleep mode.
 
uint32_t volatile TIM8LPEN: 1
 TIM8 clock enable during Sleep mode.
 
uint32_t volatile: 2
 
uint32_t volatile USART1LPEN: 1
 USART1 clock enable during Sleep mode.
 
uint32_t volatile USART6LPEN: 1
 USART6 clock enable during Sleep mode.
 
uint32_t volatile SDMMC2LPEN: 1
 SDMMC2 module clock enable during Sleep mode.
 
uint32_t volatile ADC1LPEN: 1
 ADC1 interface clock enable during Sleep mode.
 
uint32_t volatile ADC2LPEN: 1
 ADC2 interface clock enable during Sleep mode.
 
uint32_t volatile ADC3LPEN: 1
 ADC3 interface clock enable during Sleep mode.
 
uint32_t volatile SDMMC1LPEN: 1
 SDMMC1 clock enable during Sleep mode.
 
uint32_t volatile SPI1LPEN: 1
 SPI1 clock enable during Sleep mode.
 
uint32_t volatile SPI4LPEN: 1
 SPI4 clock enable during Sleep mode.
 
uint32_t volatile SYSCFGLPEN: 1
 System configuration controller clock enable during Sleep mode.
 
uint32_t volatile TIM9LPEN: 1
 TIM9 clock enable during Sleep mode.
 
uint32_t volatile TIM10LPEN: 1
 TIM10 clock enable during Sleep mode.
 
uint32_t volatile TIM11LPEN: 1
 TIM11 clock enable during Sleep mode.
 
uint32_t volatile SPI5LPEN: 1
 SPI5 clock enable during Sleep mode.
 
uint32_t volatile SPI6LPEN: 1
 SPI6 clock enable during Sleep mode.
 
uint32_t volatile SAI1LPEN: 1
 SAI1 clock enable during Sleep mode.
 
uint32_t volatile SAI2LPEN: 1
 SAI2 clock enable during Sleep mode.
 
uint32_t volatile LTDCLPEN: 1
 LTDC clock enable during Sleep mode.
 
uint32_t volatile DSILPEN: 1
 DSIHOST module clock enable during Sleep mode.
 
uint32_t volatile DFSDM1LPEN: 1
 DFSDM1 module clock enable during Sleep mode.
 
uint32_t volatile MDIOLPEN: 1
 MDIO module clock enable during Sleep mode.
 

Detailed Description

RCC APB2 peripheral clock enable in low-power mode register (RCC_APB2LPENR), chapter 5.3.19 Access: no wait state, word, half-word and byte access.

Definition at line 487 of file RCCRegisters.h.

Member Data Documentation

◆ ADC1LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::ADC1LPEN

ADC1 interface clock enable during Sleep mode.

Definition at line 495 of file RCCRegisters.h.

◆ ADC2LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::ADC2LPEN

ADC2 interface clock enable during Sleep mode.

Definition at line 496 of file RCCRegisters.h.

◆ ADC3LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::ADC3LPEN

ADC3 interface clock enable during Sleep mode.

Definition at line 497 of file RCCRegisters.h.

◆ DFSDM1LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::DFSDM1LPEN

DFSDM1 module clock enable during Sleep mode.

Definition at line 515 of file RCCRegisters.h.

◆ DSILPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::DSILPEN

DSIHOST module clock enable during Sleep mode.

Definition at line 513 of file RCCRegisters.h.

◆ LTDCLPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::LTDCLPEN

LTDC clock enable during Sleep mode.

Definition at line 512 of file RCCRegisters.h.

◆ MDIOLPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::MDIOLPEN

MDIO module clock enable during Sleep mode.

Definition at line 516 of file RCCRegisters.h.

◆ SAI1LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::SAI1LPEN

SAI1 clock enable during Sleep mode.

Definition at line 509 of file RCCRegisters.h.

◆ SAI2LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::SAI2LPEN

SAI2 clock enable during Sleep mode.

Definition at line 510 of file RCCRegisters.h.

◆ SDMMC1LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::SDMMC1LPEN

SDMMC1 clock enable during Sleep mode.

Definition at line 498 of file RCCRegisters.h.

◆ SDMMC2LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::SDMMC2LPEN

SDMMC2 module clock enable during Sleep mode.

Definition at line 494 of file RCCRegisters.h.

◆ SPI1LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::SPI1LPEN

SPI1 clock enable during Sleep mode.

Definition at line 499 of file RCCRegisters.h.

◆ SPI4LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::SPI4LPEN

SPI4 clock enable during Sleep mode.

Definition at line 500 of file RCCRegisters.h.

◆ SPI5LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::SPI5LPEN

SPI5 clock enable during Sleep mode.

Definition at line 507 of file RCCRegisters.h.

◆ SPI6LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::SPI6LPEN

SPI6 clock enable during Sleep mode.

Definition at line 508 of file RCCRegisters.h.

◆ SYSCFGLPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::SYSCFGLPEN

System configuration controller clock enable during Sleep mode.

Definition at line 501 of file RCCRegisters.h.

◆ TIM10LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::TIM10LPEN

TIM10 clock enable during Sleep mode.

Definition at line 504 of file RCCRegisters.h.

◆ TIM11LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::TIM11LPEN

TIM11 clock enable during Sleep mode.

Definition at line 505 of file RCCRegisters.h.

◆ TIM1LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::TIM1LPEN

TIM1 clock enable during Sleep mode.

Definition at line 488 of file RCCRegisters.h.

◆ TIM8LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::TIM8LPEN

TIM8 clock enable during Sleep mode.

Definition at line 489 of file RCCRegisters.h.

◆ TIM9LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::TIM9LPEN

TIM9 clock enable during Sleep mode.

Definition at line 503 of file RCCRegisters.h.

◆ USART1LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::USART1LPEN

USART1 clock enable during Sleep mode.

Definition at line 491 of file RCCRegisters.h.

◆ USART6LPEN

uint32_t volatile imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::USART6LPEN

USART6 clock enable during Sleep mode.

Definition at line 492 of file RCCRegisters.h.

◆ volatile

uint32_t imt::base::hal::stm32f767::registers::RCCRegisters::RCC_APB2LPENR::volatile
  • reserved

Definition at line 490 of file RCCRegisters.h.

The documentation for this struct was generated from the following file: