DSI.h

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// (c) IMT - Information Management Technology AG, CH-9470 Buchs, www.imt.ch.
 
#ifndef STM32F769_DSI_H
#define STM32F769_DSI_H
 
#include <Imt.Base.Core.Platform/Platform.h>
#include <Imt.Base.HAL.STM32F769/Peripherals/DSIIrqIfc.h>
#include <Imt.Base.HAL.STM32F769/Peripherals/DSITypes.h>
#include <Imt.Base.HAL.STM32F769/Registers/DSIRegisters.h>
#include <Imt.Base.HAL.STM32F769/SystemMemoryMap.h>
#include <Imt.Base.HAL.STM32F769/types.h>
 
namespace imt {
namespace base {
namespace hal {
namespace stm32f769 {
namespace peripherals {
 
class DSI {
public:
 
    struct State {
        enum Id {
            Reset = 0x00U,
            Ready = 0x01U,
            Error = 0x02U,
            Busy = 0x03U,
            Timeout = 0x04U
        };
    };
 
    union Error {
        struct Bit {
            uint32_t ACK : 1; 
            uint32_t PHY : 1; 
            uint32_t TX  : 1; 
            uint32_t RX  : 1; 
            uint32_t ECC : 1; 
            uint32_t CRC : 1; 
            uint32_t PSE : 1; 
            uint32_t EOT : 1; 
            uint32_t OVF : 1; 
            uint32_t GEN : 1; 
        };
        Bit bit;
        uint32_t all;
    };
 
    /* Exported constants, unused but kept for comletenes */
 
    // DSI_Exported_Constants DSI Exported Constants
 
    // DSI_DCS_Command DSI DCS Command
 
    //#define DSI_ENTER_IDLE_MODE       0x39U
    //#define DSI_ENTER_INVERT_MODE     0x21U
    //#define DSI_ENTER_NORMAL_MODE     0x13U
    //#define DSI_ENTER_PARTIAL_MODE    0x12U
    //#define DSI_ENTER_SLEEP_MODE      0x10U
    //#define DSI_EXIT_IDLE_MODE        0x38U
    //#define DSI_EXIT_INVERT_MODE      0x20U
    //#define DSI_EXIT_SLEEP_MODE       0x11U
    //#define DSI_GET_3D_CONTROL        0x3FU
    //#define DSI_GET_ADDRESS_MODE      0x0BU
    //#define DSI_GET_BLUE_CHANNEL      0x08U
    //#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
    //#define DSI_GET_DISPLAY_MODE      0x0DU
    //#define DSI_GET_GREEN_CHANNEL     0x07U
    //#define DSI_GET_PIXEL_FORMAT      0x0CU
    //#define DSI_GET_POWER_MODE        0x0AU
    //#define DSI_GET_RED_CHANNEL       0x06U
    //#define DSI_GET_SCANLINE          0x45U
    //#define DSI_GET_SIGNAL_MODE       0x0EU
    //#define DSI_NOP                   0x00U
    //#define DSI_READ_DDB_CONTINUE     0xA8U
    //#define DSI_READ_DDB_START        0xA1U
    //#define DSI_READ_MEMORY_CONTINUE  0x3EU
    //#define DSI_READ_MEMORY_START     0x2EU
    //#define DSI_SET_3D_CONTROL        0x3DU
    //#define DSI_SET_ADDRESS_MODE      0x36U
    //#define DSI_SET_COLUMN_ADDRESS    0x2AU
    //#define DSI_SET_DISPLAY_OFF       0x28U
    //#define DSI_SET_DISPLAY_ON        0x29U
    //#define DSI_SET_GAMMA_CURVE       0x26U
    //#define DSI_SET_PAGE_ADDRESS      0x2BU
    //#define DSI_SET_PARTIAL_COLUMNS   0x31U
    //#define DSI_SET_PARTIAL_ROWS      0x30U
    //#define DSI_SET_PIXEL_FORMAT      0x3AU
    //#define DSI_SET_SCROLL_AREA       0x33U
    //#define DSI_SET_SCROLL_START      0x37U
    //#define DSI_SET_TEAR_OFF          0x34U
    //#define DSI_SET_TEAR_ON           0x35U
    //#define DSI_SET_TEAR_SCANLINE     0x44U
    //#define DSI_SET_VSYNC_TIMING      0x40U
    //#define DSI_SOFT_RESET            0x01U
    //#define DSI_WRITE_LUT             0x2DU
    //#define DSI_WRITE_MEMORY_CONTINUE 0x3CU
    //#define DSI_WRITE_MEMORY_START    0x2CU
 
    // DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
 
    //#define DSI_DCS_SHORT_PKT_READ      0x00000006U /*!< DCS short read                     */
    //#define DSI_GEN_SHORT_PKT_READ_P0   0x00000004U /*!< Generic short read, no parameters  */
    //#define DSI_GEN_SHORT_PKT_READ_P1   0x00000014U /*!< Generic short read, one parameter  */
    //#define DSI_GEN_SHORT_PKT_READ_P2   0x00000024U /*!< Generic short read, two parameters */
 
    // DSI_Lane_Group DSI Lane Group
 
    //#define DSI_CLOCK_LANE              0x00000000U
    //#define DSI_DATA_LANES              0x00000001U
 
    // DSI_Communication_Delay DSI Communication Delay
 
    //#define DSI_SLEW_RATE_HSTX          0x00000000U
    //#define DSI_SLEW_RATE_LPTX          0x00000001U
    //#define DSI_HS_DELAY                0x00000002U
 
    // DSI_CustomLane DSI CustomLane
 
    //#define DSI_SWAP_LANE_PINS          0x00000000U
    //#define DSI_INVERT_HS_SIGNAL        0x00000001U
 
    // DSI_Lane_Select DSI Lane Select
 
    //#define DSI_CLK_LANE                0x00000000U
    //#define DSI_DATA_LANE0              0x00000001U
    //#define DSI_DATA_LANE1              0x00000002U
 
    // DSI_PHY_Timing DSI PHY Timing
 
    //#define DSI_TCLK_POST               0x00000000U
    //#define DSI_TLPX_CLK                0x00000001U
    //#define DSI_THS_EXIT                0x00000002U
    //#define DSI_TLPX_DATA               0x00000003U
    //#define DSI_THS_ZERO                0x00000004U
    //#define DSI_THS_TRAIL               0x00000005U
    //#define DSI_THS_PREPARE             0x00000006U
    //#define DSI_TCLK_ZERO               0x00000007U
    //#define DSI_TCLK_PREPARE            0x00000008U
 
    static void registerCallbacks(DSIIrqIfc* const appIrqHandler);
 
    // Initialization and Configuration Methods
 
    static Status::Id init(DSITypes::InitTypeDef& config, DSITypes::PLLConfigStruct& PLLInit);
 
    static Status::Id deInit();
 
    static void initInterrupts();
 
    // Peripheral Control Methods
 
    static void configVideoMode(DSITypes::VidCfgTypeDef const& VidCfg);
 
    static void start();
 
    static void stop();
 
    static Status::Id shortWrite(
        uint32_t const ChannelID,
        DSITypes::DsiShortPktWrite::Id const Mode,
        uint32_t const Param1,
        uint32_t const Param2);
 
    static Status::Id longWrite(
        uint32_t const ChannelID,
        DSITypes::DsiLongPktWrite::Id const Mode,
        uint32_t const NbParams,
        uint32_t const Param1,
        uint8_t const* const ParametersTable);
 
    static void refresh();
 
    static void enableWrapper();
 
    static void disableWrapper();
 
    static uint32_t IRQHandler();
 
    static void configHostTimeouts(DSITypes::HOST_TimeoutTypeDef const& hostTimeouts);
 
    static void configPhyTimer(DSITypes::PHY_TimerTypeDef const& phyTimers);
 
    static void configFlowControl(::imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCR const& flowControl);
 
    static void configErrorMonitor(Error const& activeErrors);
 
    static void configCommand(DSITypes::LPCmdTypeDef const& lpCmd);
 
    static void configAdaptedCommandMode(DSITypes::CmdCfgTypeDef const& cmdCfg);
 
    static void setGenericVCID(uint32_t const VirtualChannelID);
 
private:
 
    DSI();
 
    DSI(const DSI& other);
 
    DSI& operator=(const DSI& other);
 
    static void configPacketHeader(
        uint32_t const ChannelID,
        uint32_t const DataType,
        uint32_t const Data0,
        uint32_t const Data1);
 
    static uint32_t const TIMEOUT_VALUE = 1000U; 
 
    static Error m_ErrorCode;
    static Error m_ErrorMsk;
    static State::Id m_State;
 
    static DSIIrqIfc* s_applicationIrqHandler;
};
 
} // namespace peripherals
} // namespace stm32f769
} // namespace hal
} // namespace base
} // namespace imt
 
#endif // STM32F769_DSI_H