Imt.Base C++ API V4.1.1.0
Loading...
Searching...
No Matches
DSIRegisters.h
Go to the documentation of this file.
1// (c) IMT - Information Management Technology AG, CH-9470 Buchs, www.imt.ch.
2
3#ifndef STM32F769_DSIREGISTERS_H
4#define STM32F769_DSIREGISTERS_H
5
6#include <Imt.Base.Core.Platform/Platform.h>
7#include <Imt.Base.HAL.STM32F769/Peripherals/DSITypes.h>
8#include <Imt.Base.HAL.STM32F769/SystemMemoryMap.h>
9
10namespace imt {
11namespace base {
12namespace hal {
13namespace stm32f769 {
14namespace registers {
15
22struct DSIRegisters {
23
24 // Display Serial Interface (DSI)
25
29 struct DSI_CR {
30 uint32_t volatile EN : 1;
31 uint32_t volatile : 31;
32 };
33
37 struct DSI_CCR {
38 uint32_t volatile TXECKDIV : 8;
39 uint32_t volatile TOCKDIV : 8;
40 uint32_t volatile : 16;
41 };
42
46 struct DSI_LVCIDR {
47 uint32_t volatile VCID : 2;
48 uint32_t volatile : 30;
49 };
50
54 struct DSI_LCOLCR {
55 imt::base::hal::stm32f769::peripherals::DSITypes::RgbColorCoding::Id volatile COLC : 4;
56 uint32_t volatile : 4;
57 uint32_t volatile LPE : 1;
58 uint32_t volatile : 23;
59 };
60
64 struct DSI_LPCR {
65 uint32_t volatile DEP : 1;
66 uint32_t volatile VSP : 1;
67 uint32_t volatile HSP : 1;
68 uint32_t volatile : 29;
69 };
70
74 struct DSI_LPMCR {
75 uint32_t volatile VLPSIZE : 8;
76 uint32_t volatile : 8;
77 uint32_t volatile LPSIZE : 8;
78 uint32_t volatile : 8;
79 };
80
84 union DSI_PCR {
85 struct Bits {
86 uint32_t volatile ETTXE : 1;
87 uint32_t volatile ETRXE : 1;
88 uint32_t volatile BTAE : 1;
89 uint32_t volatile ECCRXE : 1;
90 uint32_t volatile CRCRXE : 1;
91 uint32_t volatile : 27;
92 };
93 Bits volatile bits;
94 uint32_t volatile reg;
95 };
96
100 struct DSI_GVCIDR {
101 uint32_t volatile VCID : 2;
102 uint32_t volatile : 30;
103 };
104
108 struct DSI_MCR {
109 uint32_t volatile CMDM : 1;
110 uint32_t volatile : 31;
111 };
112
116 struct DSI_VMCR {
117 uint32_t volatile VMT : 2;
118 uint32_t volatile : 6;
119 uint32_t volatile LPVSAE : 1;
120 uint32_t volatile LPVBPE : 1;
121 uint32_t volatile LPVFPE : 1;
122 uint32_t volatile LPVAE : 1;
123 uint32_t volatile LPHBPE : 1;
124 uint32_t volatile LPHFPE : 1;
125 uint32_t volatile FBTAAE : 1;
126 uint32_t volatile LPCE : 1;
127 uint32_t volatile PGE : 1;
128 uint32_t volatile : 3;
129 uint32_t volatile PGM : 1;
130 uint32_t volatile : 3;
131 uint32_t volatile PGO : 1;
132 uint32_t volatile : 7;
133 };
134
138 struct DSI_VPCR {
139 uint32_t volatile VPSIZE : 14;
140 uint32_t volatile : 18;
141 };
142
146 struct DSI_VCCR {
147 uint32_t volatile NUMC : 13;
148 uint32_t volatile : 19;
149 };
150
154 struct DSI_VNPCR {
155 uint32_t volatile NPSIZE : 13;
156 uint32_t volatile : 19;
157 };
158
162 struct DSI_VHSACR {
163 uint32_t volatile HSA : 12;
164 uint32_t volatile : 20;
165 };
166
170 struct DSI_VHBPCR {
171 uint32_t volatile HBP : 12;
172 uint32_t volatile : 20;
173 };
174
178 struct DSI_VLCR {
179 uint32_t volatile HLINE : 15;
180 uint32_t volatile : 17;
181 };
182
186 struct DSI_VVSACR {
187 uint32_t volatile VSA : 10;
188 uint32_t volatile : 22;
189 };
190
194 struct DSI_VVBPCR {
195 uint32_t volatile VBP : 10;
196 uint32_t volatile : 22;
197 };
198
202 struct DSI_VVFPCR {
203 uint32_t volatile VFP : 10;
204 uint32_t volatile : 22;
205 };
206
210 struct DSI_VVACR {
211 uint32_t volatile VA : 14;
212 uint32_t volatile : 18;
213 };
214
218 struct DSI_LCCR {
219 uint32_t volatile CMDSIZE : 16;
220 uint32_t volatile : 16;
221 };
222
226 struct DSI_CMCR {
227 uint32_t volatile TEARE : 1;
228 uint32_t volatile ARE : 1;
229 uint32_t volatile : 6;
230 uint32_t volatile GSW0TX : 1;
231 uint32_t volatile GSW1TX : 1;
232 uint32_t volatile GSW2TX : 1;
233 uint32_t volatile GSR0TX : 1;
234 uint32_t volatile GSR1TX : 1;
235 uint32_t volatile GSR2TX : 1;
236 uint32_t volatile GLWTX : 1;
237 uint32_t volatile : 1;
238 uint32_t volatile DSW0TX : 1;
239 uint32_t volatile DSW1TX : 1;
240 uint32_t volatile DSR0TX : 1;
241 uint32_t volatile DLWTX : 1;
242 uint32_t volatile : 4;
243 uint32_t volatile MRDPS : 1;
244 uint32_t volatile : 7;
245 };
246
250 union DSI_GHCR {
251 struct Fields {
252 uint32_t volatile DT : 6;
253 uint32_t volatile VCID : 2;
254 uint32_t volatile WCLSB : 8;
255 uint32_t volatile WCMSB : 8;
256 uint32_t volatile : 8;
257 };
258 Fields volatile fields;
259 uint32_t volatile reg;
260 };
261
265 union DSI_GPDR {
266 struct Fields {
267 uint32_t volatile DATA1 : 8;
268 uint32_t volatile DATA2 : 8;
269 uint32_t volatile DATA3 : 8;
270 uint32_t volatile DATA4 : 8;
271 };
272 Fields volatile fields;
273 uint32_t volatile reg;
274 };
275
279 union DSI_GPSR {
280 struct Fields {
281 uint32_t volatile CMDFE : 1;
282 uint32_t volatile CMDFF : 1;
283 uint32_t volatile PWRFE : 1;
284 uint32_t volatile PWRFF : 1;
285 uint32_t volatile PRDFE : 1;
286 uint32_t volatile PRDFF : 1;
287 uint32_t volatile RCB : 1;
288 uint32_t volatile : 25;
289 };
290 Fields volatile fields;
291 uint32_t volatile reg;
292 };
293
297 struct DSI_TCCR0 {
298 uint32_t volatile LPRX_TOCNT : 16;
299 uint32_t volatile HSTX_TOCNT : 16;
300 };
301
305 struct DSI_TCCR1 {
306 uint32_t volatile HSRD_TOCNT : 16;
307 uint32_t volatile : 16;
308 };
309
313 struct DSI_TCCR2 {
314 uint32_t volatile LPRD_TOCNT : 16;
315 uint32_t volatile : 16;
316 };
317
321 struct DSI_TCCR3 {
322 uint32_t volatile HSWR_TOCNT : 16;
323 uint32_t volatile : 8;
324 uint32_t volatile PM : 1;
325 uint32_t volatile : 7;
326 };
327
331 struct DSI_TCCR4 {
332 uint32_t volatile LPWR_TOCNT : 16;
333 uint32_t volatile : 16;
334 };
335
339 struct DSI_TCCR5 {
340 uint32_t volatile BTA_TOCNT : 16;
341 uint32_t volatile : 16;
342 };
343
347 struct DSI_TDCR {
348 uint32_t volatile THREEDM : 2;
349 uint32_t volatile THREE3DF : 2;
350 uint32_t volatile SVS : 1;
351 uint32_t volatile RF : 1;
352 uint32_t volatile : 10;
353 uint32_t volatile S3DC : 1;
354 uint32_t volatile : 15;
355 };
356
360 struct DSI_CLCR {
361 uint32_t volatile DPCC : 1;
362 uint32_t volatile ACR : 1;
363 uint32_t volatile : 30;
364 };
365
369 struct DSI_CLTCR {
370 uint32_t volatile LP2HS_TIME : 10;
371 uint32_t volatile : 6;
372 uint32_t volatile HS2LP_TIME : 10;
373 uint32_t volatile : 6;
374 };
375
379 struct DSI_DLTCR {
380 uint32_t volatile MRD_TIME : 15;
381 uint32_t volatile : 1;
382 uint32_t volatile LP2HS_TIME : 8;
383 uint32_t volatile HS2LP_TIME : 8;
384 };
385
389 struct DSI_PCTLR {
390 uint32_t volatile : 1;
391 uint32_t volatile DEN : 1;
392 uint32_t volatile CKE : 1;
393 uint32_t volatile : 29;
394 };
395
399 struct DSI_PCONFR {
400 uint32_t volatile NL : 2;
401 uint32_t volatile : 6;
402 uint32_t volatile SW_TIME : 8;
403 uint32_t volatile : 16;
404 };
405
409 union DSI_PUCR {
410 struct Bits {
411 uint32_t volatile URCL : 1;
412 uint32_t volatile UECL : 1;
413 uint32_t volatile URDL : 1;
414 uint32_t volatile UEDL : 1;
415 uint32_t volatile : 28;
416 };
417 Bits volatile bits;
418 uint32_t volatile reg;
419 };
420
424 struct DSI_PTTCR {
425 uint32_t volatile TX_TRIG : 4;
426 uint32_t volatile : 28;
427 };
428
432 struct DSI_PSR {
433 uint32_t volatile : 1;
434 uint32_t volatile PD : 1;
435 uint32_t volatile PSSC : 1;
436 uint32_t volatile UANC : 1;
437 uint32_t volatile PSS0 : 1;
438 uint32_t volatile UAN0 : 1;
439 uint32_t volatile RUE0 : 1;
440 uint32_t volatile PSS1 : 1;
441 uint32_t volatile UAN1 : 1;
442 uint32_t volatile : 23;
443 };
444
448 union DSI_ISR0 {
449 struct Bits {
450 uint32_t volatile AE0 : 1;
451 uint32_t volatile AE1 : 1;
452 uint32_t volatile AE2 : 1;
453 uint32_t volatile AE3 : 1;
454 uint32_t volatile AE4 : 1;
455 uint32_t volatile AE5 : 1;
456 uint32_t volatile AE6 : 1;
457 uint32_t volatile AE7 : 1;
458 uint32_t volatile AE8 : 1;
459 uint32_t volatile AE9 : 1;
460 uint32_t volatile AE10 : 1;
461 uint32_t volatile AE11 : 1;
462 uint32_t volatile AE12 : 1;
463 uint32_t volatile AE13 : 1;
464 uint32_t volatile AE14 : 1;
465 uint32_t volatile AE15 : 1;
466 uint32_t volatile PE0 : 1;
467 uint32_t volatile PE1 : 1;
468 uint32_t volatile PE2 : 1;
469 uint32_t volatile PE3 : 1;
470 uint32_t volatile PE4 : 1;
471 uint32_t volatile : 11;
472 };
473 struct Fields {
474 uint32_t volatile AE : 16;
475 uint32_t volatile PE : 5;
476 uint32_t volatile : 11;
477 };
478 Bits volatile bits;
479 Fields volatile fields;
480 uint32_t volatile reg;
481 };
482
486 union DSI_ISR1 {
487 struct Bits {
488 uint32_t volatile TOHSTX : 1;
489 uint32_t volatile TOLPRX : 1;
490 uint32_t volatile ECCSE : 1;
491 uint32_t volatile ECCME : 1;
492 uint32_t volatile CRCE : 1;
493 uint32_t volatile PSE : 1;
494 uint32_t volatile EOTPE : 1;
495 uint32_t volatile LPWRE : 1;
496 uint32_t volatile GCWRE : 1;
497 uint32_t volatile GPWRE : 1;
498 uint32_t volatile GPTXE : 1;
499 uint32_t volatile GPRDE : 1;
500 uint32_t volatile GPRXE : 1;
501 uint32_t volatile : 19;
502 };
503 Bits volatile bits;
504 uint32_t volatile reg;
505 };
506
510 union DSI_IER0 {
511 struct Bits {
512 uint32_t volatile AE0IE : 1;
513 uint32_t volatile AE1IE : 1;
514 uint32_t volatile AE2IE : 1;
515 uint32_t volatile AE3IE : 1;
516 uint32_t volatile AE4IE : 1;
517 uint32_t volatile AE5IE : 1;
518 uint32_t volatile AE6IE : 1;
519 uint32_t volatile AE7IE : 1;
520 uint32_t volatile AE8IE : 1;
521 uint32_t volatile AE9IE : 1;
522 uint32_t volatile AE10IE : 1;
523 uint32_t volatile AE11IE : 1;
524 uint32_t volatile AE12IE : 1;
525 uint32_t volatile AE13IE : 1;
526 uint32_t volatile AE14IE : 1;
527 uint32_t volatile AE15IE : 1;
528 uint32_t volatile PE0IE : 1;
529 uint32_t volatile PE1IE : 1;
530 uint32_t volatile PE2IE : 1;
531 uint32_t volatile PE3IE : 1;
532 uint32_t volatile PE4IE : 1;
533 uint32_t volatile : 11;
534 };
535 struct Fields {
536 uint32_t volatile AEIE : 16;
537 uint32_t volatile PEIE : 5;
538 uint32_t volatile : 11;
539 };
540 Bits volatile bits;
541 Fields volatile fields;
542 uint32_t volatile reg;
543 };
544
548 union DSI_IER1 {
549 struct Fields {
550 uint32_t volatile TOHSTXIE : 1;
551 uint32_t volatile TOLPRXIE : 1;
552 uint32_t volatile ECCSEIE : 1;
553 uint32_t volatile ECCMEIE : 1;
554 uint32_t volatile CRCEIE : 1;
555 uint32_t volatile PSEIE : 1;
556 uint32_t volatile EOTPEIE : 1;
557 uint32_t volatile LPWREIE : 1;
558 uint32_t volatile GCWREIE : 1;
559 uint32_t volatile GPWREIE : 1;
560 uint32_t volatile GPTXEIE : 1;
561 uint32_t volatile GPRDEIE : 1;
562 uint32_t volatile GPRXEIE : 1;
563 uint32_t volatile : 19;
564 };
565 Fields volatile fields;
566 uint32_t volatile reg;
567 };
568
572 struct DSI_FIR0 {
573 uint32_t volatile FAE0 : 1;
574 uint32_t volatile FAE1 : 1;
575 uint32_t volatile FAE2 : 1;
576 uint32_t volatile FAE3 : 1;
577 uint32_t volatile FAE4 : 1;
578 uint32_t volatile FAE5 : 1;
579 uint32_t volatile FAE6 : 1;
580 uint32_t volatile FAE7 : 1;
581 uint32_t volatile FAE8 : 1;
582 uint32_t volatile FAE9 : 1;
583 uint32_t volatile FAE10 : 1;
584 uint32_t volatile FAE11 : 1;
585 uint32_t volatile FAE12 : 1;
586 uint32_t volatile FAE13 : 1;
587 uint32_t volatile FAE14 : 1;
588 uint32_t volatile FAE15 : 1;
589 uint32_t volatile FPE0 : 1;
590 uint32_t volatile FPE1 : 1;
591 uint32_t volatile FPE2 : 1;
592 uint32_t volatile FPE3 : 1;
593 uint32_t volatile FPE4 : 1;
594 uint32_t volatile : 11;
595 };
596
600 struct DSI_FIR1 {
601 uint32_t volatile FTOHSTX : 1;
602 uint32_t volatile FTOLPRX : 1;
603 uint32_t volatile FECCSE : 1;
604 uint32_t volatile FECCME : 1;
605 uint32_t volatile FCRCE : 1;
606 uint32_t volatile FPSE : 1;
607 uint32_t volatile FEOTPE : 1;
608 uint32_t volatile FLPWRE : 1;
609 uint32_t volatile FGCWRE : 1;
610 uint32_t volatile FGPWRE : 1;
611 uint32_t volatile FGPTXE : 1;
612 uint32_t volatile FGPRDE : 1;
613 uint32_t volatile FGPRXE : 1;
614 uint32_t volatile : 19;
615 };
616
620 struct DSI_VSCR {
621 uint32_t volatile EN : 1;
622 uint32_t volatile : 7;
623 uint32_t volatile UR : 1;
624 uint32_t volatile : 23;
625 };
626
630 struct DSI_LCVCIDR {
631 uint32_t volatile VCID : 2;
632 uint32_t volatile : 30;
633 };
634
638 struct DSI_LCCCR {
639 imt::base::hal::stm32f769::peripherals::DSITypes::RgbColorCoding::Id volatile COLC : 4;
640 uint32_t volatile : 4;
641 uint32_t volatile LPE : 1;
642 uint32_t volatile : 23;
643 };
644
648 struct DSI_LPMCCR {
649 uint32_t volatile VLPSIZE : 8;
650 uint32_t volatile : 8;
651 uint32_t volatile LPSIZE : 8;
652 uint32_t volatile : 8;
653 };
654
658 struct DSI_VMCCR {
659 uint32_t volatile VMT : 2;
660 uint32_t volatile LPVSAE : 1;
661 uint32_t volatile LPVBPE : 1;
662 uint32_t volatile LPVFPE : 1;
663 uint32_t volatile LPVAE : 1;
664 uint32_t volatile LPHBPE : 1;
665 uint32_t volatile LPHFE : 1;
666 uint32_t volatile FBTAAE : 1;
667 uint32_t volatile LPCE : 1;
668 uint32_t volatile : 22;
669 };
670
674 struct DSI_VPCCR {
675 uint32_t volatile VPSIZE : 14;
676 uint32_t volatile : 18;
677 };
678
682 struct DSI_VCCCR {
683 uint32_t volatile NUMC : 13;
684 uint32_t volatile : 19;
685 };
686
690 struct DSI_VNPCCR {
691 uint32_t volatile NPSIZE : 13;
692 uint32_t volatile : 19;
693 };
694
698 struct DSI_VHSACCR {
699 uint32_t volatile HSA : 12;
700 uint32_t volatile : 20;
701 };
702
706 struct DSI_VHBPCCR {
707 uint32_t volatile HBP : 12;
708 uint32_t volatile : 20;
709 };
710
714 struct DSI_VLCCR {
715 uint32_t volatile HLINE : 15;
716 uint32_t volatile : 17;
717 };
718
722 struct DSI_VVSACCR {
723 uint32_t volatile VSA : 10;
724 uint32_t volatile : 22;
725 };
726
730 struct DSI_VVBPCCR {
731 uint32_t volatile VBP : 10;
732 uint32_t volatile : 22;
733 };
734
738 struct DSI_VVFPCCR {
739 uint32_t volatile VFP : 10;
740 uint32_t volatile : 22;
741 };
742
746 struct DSI_VVACCR {
747 uint32_t volatile VA : 14;
748 uint32_t volatile : 18;
749 };
750
754 struct DSI_TDCCR {
755 uint32_t volatile THREEDM : 2;
756 uint32_t volatile THREE3DF : 2;
757 uint32_t volatile SVS : 1;
758 uint32_t volatile RF : 1;
759 uint32_t volatile : 10;
760 uint32_t volatile S3DC : 1;
761 uint32_t volatile : 15;
762 };
763
764 //==========================================================================
766 //==========================================================================
767
771 struct DSI_WCFGR {
772 uint32_t volatile DSIM : 1;
773 imt::base::hal::stm32f769::peripherals::DSITypes::RgbColorCoding::Id volatile COLMUX : 3;
774 uint32_t volatile TESRC : 1;
775 uint32_t volatile TEPOL : 1;
776 uint32_t volatile AR : 1;
777 uint32_t volatile VSPOL : 1;
778 uint32_t volatile : 24;
779 };
780
784 struct DSI_WCR {
785 uint32_t volatile COLM : 1;
786 uint32_t volatile SHTDN : 1;
787 uint32_t volatile LTDCEN : 1;
788 uint32_t volatile DSIEN : 1;
789 uint32_t volatile : 28;
790 };
791
795 struct DSI_WIER {
796 uint32_t volatile TE : 1;
797 uint32_t volatile ER : 1;
798 uint32_t volatile : 7;
799 uint32_t volatile PLLL : 1;
800 uint32_t volatile PLLU : 1;
801 uint32_t volatile : 2;
802 uint32_t volatile RR : 1;
803 uint32_t volatile : 18;
804 };
805
809 struct DSI_WISR {
810 uint32_t volatile TE : 1;
811 uint32_t volatile ER : 1;
812 uint32_t volatile BUSY : 1;
813 uint32_t volatile : 5;
814 uint32_t volatile PLLLS : 1;
815 uint32_t volatile PLLL : 1;
816 uint32_t volatile PLLU : 1;
817 uint32_t volatile : 1;
818 uint32_t volatile RRS : 1;
819 uint32_t volatile RR : 1;
820 uint32_t volatile : 18;
821 };
822
826 struct DSI_WIFCR {
827 uint32_t volatile TE : 1;
828 uint32_t volatile ER : 1;
829 uint32_t volatile : 7;
830 uint32_t volatile PLLL : 1;
831 uint32_t volatile PLLU : 1;
832 uint32_t volatile : 2;
833 uint32_t volatile RR : 1;
834 uint32_t volatile : 18;
835 };
836
840 struct DSI_WPCR0 {
841 uint32_t volatile UIX4 : 6;
842 FunctionalState::Id volatile SWCL : 1;
843 uint32_t volatile SWDL0 : 1;
844 uint32_t volatile SWDL1 : 1;
845 uint32_t volatile HSICL : 1;
846 uint32_t volatile HSIDL0 : 1;
847 uint32_t volatile HSIDL1 : 1;
848 uint32_t volatile FTXSMCL : 1;
849 uint32_t volatile FTXSMDL : 1;
850 uint32_t volatile CDOFFDL : 1;
851 uint32_t volatile : 1;
852 uint32_t volatile TDDL : 1;
853 uint32_t volatile : 1;
854 uint32_t volatile PDEN : 1;
855 uint32_t volatile TCLKPREPEN : 1;
856 uint32_t volatile TCLKZEROEN : 1;
857 uint32_t volatile THSPREPEN : 1;
858 uint32_t volatile THSTRAILEN : 1;
859 uint32_t volatile THSZEROEN : 1;
860 uint32_t volatile TLPXDEN : 1;
861 uint32_t volatile THSEXITEN : 1;
862 uint32_t volatile TLPXCEN : 1;
863 uint32_t volatile TCLKPOSTEN : 1;
864 uint32_t volatile : 4;
865 };
866
870 struct DSI_WPCR1 {
871 uint32_t volatile HSTXDCL : 2;
872 uint32_t volatile HSTXDDL : 2;
873 uint32_t volatile : 2;
874 uint32_t volatile LPSRCCL : 2;
875 uint32_t volatile LPSRCDL : 2;
876 uint32_t volatile : 2;
877 uint32_t volatile SDDC : 1;
878 uint32_t volatile : 1;
879 uint32_t volatile LPRXVCDL : 2;
880 uint32_t volatile HSTXSRCCL : 2;
881 uint32_t volatile HSTXSRCDL : 2;
882 uint32_t volatile : 2;
883 uint32_t volatile FLPRXLPM : 1;
884 uint32_t volatile : 2;
885 uint32_t volatile LPRXFT : 2;
886 uint32_t volatile : 5;
887 };
888
892 struct DSI_WPCR2 {
893 uint32_t volatile TCLKPREP : 8;
894 uint32_t volatile TCLKZERO : 8;
895 uint32_t volatile THSPREP : 8;
896 uint32_t volatile THSTRAIL : 8;
897 };
898
902 struct DSI_WPCR3 {
903 uint32_t volatile THSZERO : 8;
904 uint32_t volatile TLPXD : 8;
905 uint32_t volatile THSEXIT : 8;
906 uint32_t volatile TLPXC : 8;
907 };
908
912 struct DSI_WPCR4 {
913 uint32_t volatile TCLKPOST : 8;
914 uint32_t volatile : 24;
915 };
916
920 struct DSI_WRPCR {
921 uint32_t volatile PLLEN : 1;
922 uint32_t volatile : 1;
923 uint32_t volatile NDIV : 7;
924 uint32_t volatile : 2;
925 uint32_t volatile IDF : 4;
926 uint32_t volatile : 1;
927 uint32_t volatile ODF : 2;
928 uint32_t volatile : 6;
929 uint32_t volatile REGEN : 1;
930 uint32_t volatile : 7;
931 };
932
936 static DSIRegisters& getInstance() {
937 return *reinterpret_cast<DSIRegisters*>(SystemMemoryMap::DSI_HOST_BASE);
938 };
939
940 // Registers
941 uint32_t volatile VR;
942 volatile DSI_CR CR;
943 volatile DSI_CCR CCR;
944 volatile DSI_LVCIDR LVCIDR;
945 volatile DSI_LCOLCR LCOLCR;
946 volatile DSI_LPCR LPCR;
947 volatile DSI_LPMCR LPMCR;
948 uint32_t volatile reserved0[4];
949 volatile DSI_PCR PCR;
950 volatile DSI_GVCIDR GVCIDR;
951 volatile DSI_MCR MCR;
952 volatile DSI_VMCR VMCR;
953 volatile DSI_VPCR VPCR;
954 volatile DSI_VCCR VCCR;
955 volatile DSI_VNPCR VNPCR;
956 volatile DSI_VHSACR VHSACR;
957 volatile DSI_VHBPCR VHBPCR;
958 volatile DSI_VLCR VLCR;
959 volatile DSI_VVSACR VVSACR;
960 volatile DSI_VVBPCR VVBPCR;
961 volatile DSI_VVFPCR VVFPCR;
962 volatile DSI_VVACR VVACR;
963 volatile DSI_LCCR LCCR;
964 volatile DSI_CMCR CMCR;
965 volatile DSI_GHCR GHCR;
966 volatile DSI_GPDR GPDR;
967 volatile DSI_GPSR GPSR;
968 volatile DSI_TCCR0 TCCR0;
969 volatile DSI_TCCR1 TCCR1;
970 volatile DSI_TCCR2 TCCR2;
971 volatile DSI_TCCR3 TCCR3;
972 volatile DSI_TCCR4 TCCR4;
973 volatile DSI_TCCR5 TCCR5;
974 volatile DSI_TDCR TDCR;
975 volatile DSI_CLCR CLCR;
976 volatile DSI_CLTCR CLTCR;
977 volatile DSI_DLTCR DLTCR;
978 volatile DSI_PCTLR PCTLR;
979 volatile DSI_PCONFR PCONFR;
980 volatile DSI_PUCR PUCR;
981 volatile DSI_PTTCR PTTCR;
982 volatile DSI_PSR PSR;
983 uint32_t volatile reserved1[2];
984 volatile DSI_ISR0 ISR0;
985 volatile DSI_ISR1 ISR1;
986 volatile DSI_IER0 IER0;
987 volatile DSI_IER1 IER1;
988 uint32_t volatile reserved2[3];
989 volatile DSI_FIR0 FIR0;
990 volatile DSI_FIR1 FIR1;
991 uint32_t volatile reserved3[8];
992 volatile DSI_VSCR VSCR;
993 uint32_t volatile reserved4[2];
994 volatile DSI_LCVCIDR LCVCIDR;
995 volatile DSI_LCCCR LCCCR;
996 uint32_t volatile reserved5;
997 volatile DSI_LPMCCR LPMCCR;
998 uint32_t volatile reserved6[7];
999 volatile DSI_VMCCR VMCCR;
1000 volatile DSI_VPCCR VPCCR;
1001 volatile DSI_VCCCR VCCCR;
1002 volatile DSI_VNPCCR VNPCCR;
1003 volatile DSI_VHSACCR VHSACCR;
1004 volatile DSI_VHBPCCR VHBPCCR;
1005 volatile DSI_VLCCR VLCCR;
1006 volatile DSI_VVSACCR VVSACCR;
1007 volatile DSI_VVBPCCR VVBPCCR;
1008 volatile DSI_VVFPCCR VVFPCCR;
1009 volatile DSI_VVACCR VVACCR;
1010 uint32_t volatile reserved7[11];
1011 volatile DSI_TDCCR TDCCR;
1012 uint32_t volatile reserved8[155];
1013 volatile DSI_WCFGR WCFGR;
1014 volatile DSI_WCR WCR;
1015 volatile DSI_WIER WIER;
1016 volatile DSI_WISR WISR;
1017 volatile DSI_WIFCR WIFCR;
1018 uint32_t volatile reserved9;
1019 volatile DSI_WPCR0 WPCR0;
1020 volatile DSI_WPCR1 WPCR1;
1021 volatile DSI_WPCR2 WPCR2;
1022 volatile DSI_WPCR3 WPCR3;
1023 volatile DSI_WPCR4 WPCR4;
1024 uint32_t volatile reserved10;
1025 volatile DSI_WRPCR WRPCR;
1026
1027private:
1028
1032 DSIRegisters();
1033
1037 DSIRegisters(DSIRegisters const& other);
1038
1042 DSIRegisters& operator=(DSIRegisters const& other);
1043};
1044
1045} // namespace registers
1046} // namespace stm32f769
1047} // namespace hal
1048} // namespace base
1049} // namespace imt
1050
1051#endif // STM32F769_DSIREGISTERS_H
imt
This is a application specific file which is used to configure Imt.Base.Core.Math.
Definition MathConfigApp.h:15
uint32_t
unsigned __int32 uint32_t
Definition stdint.h:64
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CCR
DSI Host Clock Control Register (DSI_CCR), chapter 20.15.3.
Definition DSIRegisters.h:37
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CCR::TOCKDIV
uint32_t volatile TOCKDIV
Timeout Clock Division.
Definition DSIRegisters.h:39
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CCR::TXECKDIV
uint32_t volatile TXECKDIV
TX Escape Clock Division.
Definition DSIRegisters.h:38
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CCR::volatile
uint32_t volatile
Definition DSIRegisters.h:40
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CLCR
DSI Host Clock Lane Configuration Register (DSI_CLCR), chapter 20.15.33.
Definition DSIRegisters.h:360
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CLCR::ACR
uint32_t volatile ACR
Automatic Clocklane Control.
Definition DSIRegisters.h:362
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CLCR::DPCC
uint32_t volatile DPCC
D-PHY Clock Control.
Definition DSIRegisters.h:361
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CLCR::volatile
uint32_t volatile
Definition DSIRegisters.h:363
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CLTCR
DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR), chapter 20.15.34.
Definition DSIRegisters.h:369
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CLTCR::LP2HS_TIME
uint32_t volatile LP2HS_TIME
Low-Power to High-Speed Time.
Definition DSIRegisters.h:370
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CLTCR::HS2LP_TIME
uint32_t volatile HS2LP_TIME
High-Speed to Low-Power Time.
Definition DSIRegisters.h:372
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CLTCR::volatile
uint32_t volatile
Definition DSIRegisters.h:371
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR
DSI Host Command mode Configuration Register (DSI_CMCR), chapter 20.15.23.
Definition DSIRegisters.h:226
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::GSW2TX
uint32_t volatile GSW2TX
Generic Short Write Two parameters Transmission.
Definition DSIRegisters.h:232
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::TEARE
uint32_t volatile TEARE
Tearing Effect Acknowledge Request Enable.
Definition DSIRegisters.h:227
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::GSR0TX
uint32_t volatile GSR0TX
Generic Short Read Zero parameters Transmission.
Definition DSIRegisters.h:233
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::DSW1TX
uint32_t volatile DSW1TX
DCS Short Write One parameter Transmission.
Definition DSIRegisters.h:239
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::GSW0TX
uint32_t volatile GSW0TX
Generic Short Write Zero parameters Transmission.
Definition DSIRegisters.h:230
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::DSW0TX
uint32_t volatile DSW0TX
DCS Short Write Zero parameter Transmission.
Definition DSIRegisters.h:238
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::GSR1TX
uint32_t volatile GSR1TX
Generic Short Read One parameters Transmission.
Definition DSIRegisters.h:234
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::GSW1TX
uint32_t volatile GSW1TX
Generic Short Write One parameters Transmission.
Definition DSIRegisters.h:231
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::volatile
uint32_t volatile
Definition DSIRegisters.h:229
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::GLWTX
uint32_t volatile GLWTX
Generic Long Write Transmission.
Definition DSIRegisters.h:236
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::DSR0TX
uint32_t volatile DSR0TX
DCS Short Read Zero parameter Transmission.
Definition DSIRegisters.h:240
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::MRDPS
uint32_t volatile MRDPS
Maximum Read Packet Size.
Definition DSIRegisters.h:243
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::DLWTX
uint32_t volatile DLWTX
DCS Long Write Transmission.
Definition DSIRegisters.h:241
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::GSR2TX
uint32_t volatile GSR2TX
Generic Short Read Two parameters Transmission.
Definition DSIRegisters.h:235
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CMCR::ARE
uint32_t volatile ARE
Acknowledge Request Enable.
Definition DSIRegisters.h:228
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CR
DSI Host Control Register (DSI_CR), chapter 20.15.2.
Definition DSIRegisters.h:29
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CR::EN
uint32_t volatile EN
dsi host controller enable
Definition DSIRegisters.h:30
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_CR::volatile
uint32_t volatile
Definition DSIRegisters.h:31
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_DLTCR
DSI Host Data Lane Timer Configuration Register (DSI_DLTCR), chapter 20.15.35.
Definition DSIRegisters.h:379
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_DLTCR::MRD_TIME
uint32_t volatile MRD_TIME
Maximum Read Time.
Definition DSIRegisters.h:380
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_DLTCR::HS2LP_TIME
uint32_t volatile HS2LP_TIME
High-Speed To Low-Power Time.
Definition DSIRegisters.h:383
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_DLTCR::volatile
uint32_t volatile
Definition DSIRegisters.h:381
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_DLTCR::LP2HS_TIME
uint32_t volatile LP2HS_TIME
Low-Power To High-Speed Time.
Definition DSIRegisters.h:382
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0
DSI Host Force Interrupt Register 0 (DSI_FIR0), chapter 20.15.45.
Definition DSIRegisters.h:572
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE10
uint32_t volatile FAE10
Force Acknowledge Error 10.
Definition DSIRegisters.h:583
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE14
uint32_t volatile FAE14
Force Acknowledge Error 14.
Definition DSIRegisters.h:587
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE8
uint32_t volatile FAE8
Force Acknowledge Error 8.
Definition DSIRegisters.h:581
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE7
uint32_t volatile FAE7
Force Acknowledge Error 7.
Definition DSIRegisters.h:580
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FPE0
uint32_t volatile FPE0
Force PHY Error 0.
Definition DSIRegisters.h:589
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE13
uint32_t volatile FAE13
Force Acknowledge Error 13.
Definition DSIRegisters.h:586
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FPE4
uint32_t volatile FPE4
Force PHY Error 4.
Definition DSIRegisters.h:593
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE4
uint32_t volatile FAE4
Force Acknowledge Error 4.
Definition DSIRegisters.h:577
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE6
uint32_t volatile FAE6
Force Acknowledge Error 6.
Definition DSIRegisters.h:579
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE9
uint32_t volatile FAE9
Force Acknowledge Error 9.
Definition DSIRegisters.h:582
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FPE2
uint32_t volatile FPE2
Force PHY Error 2.
Definition DSIRegisters.h:591
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE2
uint32_t volatile FAE2
Force Acknowledge Error 2.
Definition DSIRegisters.h:575
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE1
uint32_t volatile FAE1
Force Acknowledge Error 1.
Definition DSIRegisters.h:574
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FPE3
uint32_t volatile FPE3
Force PHY Error 3.
Definition DSIRegisters.h:592
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FPE1
uint32_t volatile FPE1
Force PHY Error 1.
Definition DSIRegisters.h:590
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE5
uint32_t volatile FAE5
Force Acknowledge Error 5.
Definition DSIRegisters.h:578
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE11
uint32_t volatile FAE11
Force Acknowledge Error 11.
Definition DSIRegisters.h:584
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE12
uint32_t volatile FAE12
Force Acknowledge Error 12.
Definition DSIRegisters.h:585
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE3
uint32_t volatile FAE3
Force Acknowledge Error 3.
Definition DSIRegisters.h:576
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::volatile
uint32_t volatile
Definition DSIRegisters.h:594
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE15
uint32_t volatile FAE15
Force Acknowledge Error 15.
Definition DSIRegisters.h:588
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR0::FAE0
uint32_t volatile FAE0
Force Acknowledge Error 0.
Definition DSIRegisters.h:573
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1
DSI Host Force Interrupt Register 1 (DSI_FIR1), chapter 20.15.46.
Definition DSIRegisters.h:600
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FECCME
uint32_t volatile FECCME
Force ECC Multi-bit Error.
Definition DSIRegisters.h:604
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::volatile
uint32_t volatile
Definition DSIRegisters.h:614
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FPSE
uint32_t volatile FPSE
Force Packet Size Error.
Definition DSIRegisters.h:606
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FGPRXE
uint32_t volatile FGPRXE
Force Generic Payload Receive Error.
Definition DSIRegisters.h:613
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FTOHSTX
uint32_t volatile FTOHSTX
Force Timeout High-Speed Transmission.
Definition DSIRegisters.h:601
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FECCSE
uint32_t volatile FECCSE
Force ECC Single-bit Error.
Definition DSIRegisters.h:603
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FGPWRE
uint32_t volatile FGPWRE
Force Generic Payload Write Error.
Definition DSIRegisters.h:610
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FGPRDE
uint32_t volatile FGPRDE
Force Generic Payload Read Error.
Definition DSIRegisters.h:612
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FGPTXE
uint32_t volatile FGPTXE
Force Generic Payload Transmit Error.
Definition DSIRegisters.h:611
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FTOLPRX
uint32_t volatile FTOLPRX
Force Timeout Low-Power Reception.
Definition DSIRegisters.h:602
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FGCWRE
uint32_t volatile FGCWRE
Force Generic Command Write Error.
Definition DSIRegisters.h:609
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FEOTPE
uint32_t volatile FEOTPE
Force EoTp Error.
Definition DSIRegisters.h:607
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FCRCE
uint32_t volatile FCRCE
Force CRC Error.
Definition DSIRegisters.h:605
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_FIR1::FLPWRE
uint32_t volatile FLPWRE
Force LTDC Payload Write Error.
Definition DSIRegisters.h:608
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GHCR::Fields
Definition DSIRegisters.h:251
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GHCR::Fields::volatile
uint32_t volatile
Definition DSIRegisters.h:256
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GHCR::Fields::WCLSB
uint32_t volatile WCLSB
WordCount LSB.
Definition DSIRegisters.h:254
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GHCR::Fields::VCID
uint32_t volatile VCID
Channel.
Definition DSIRegisters.h:253
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GHCR::Fields::DT
uint32_t volatile DT
Type.
Definition DSIRegisters.h:252
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GHCR::Fields::WCMSB
uint32_t volatile WCMSB
WordCount MSB.
Definition DSIRegisters.h:255
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPDR::Fields
Definition DSIRegisters.h:266
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPDR::Fields::DATA3
uint32_t volatile DATA3
Payload Byte 3.
Definition DSIRegisters.h:269
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPDR::Fields::DATA1
uint32_t volatile DATA1
Payload Byte 1.
Definition DSIRegisters.h:267
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPDR::Fields::DATA4
uint32_t volatile DATA4
Payload Byte 4.
Definition DSIRegisters.h:270
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPDR::Fields::DATA2
uint32_t volatile DATA2
Payload Byte 2.
Definition DSIRegisters.h:268
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPSR::Fields
Definition DSIRegisters.h:280
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPSR::Fields::CMDFF
uint32_t volatile CMDFF
Command FIFO Full.
Definition DSIRegisters.h:282
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPSR::Fields::PRDFF
uint32_t volatile PRDFF
Payload Read FIFO Full.
Definition DSIRegisters.h:286
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPSR::Fields::PRDFE
uint32_t volatile PRDFE
Payload Read FIFO Empty.
Definition DSIRegisters.h:285
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPSR::Fields::PWRFF
uint32_t volatile PWRFF
Payload Write FIFO Full.
Definition DSIRegisters.h:284
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPSR::Fields::CMDFE
uint32_t volatile CMDFE
Command FIFO Empty.
Definition DSIRegisters.h:281
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPSR::Fields::RCB
uint32_t volatile RCB
Read Command Busy.
Definition DSIRegisters.h:287
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPSR::Fields::volatile
uint32_t volatile
Definition DSIRegisters.h:288
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPSR::Fields::PWRFE
uint32_t volatile PWRFE
Payload Write FIFO Empty.
Definition DSIRegisters.h:283
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GVCIDR
DSI Host Generic VCID Register (DSI_GVCIDR), chapter 20.15.9.
Definition DSIRegisters.h:100
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GVCIDR::volatile
uint32_t volatile
Definition DSIRegisters.h:102
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GVCIDR::VCID
uint32_t volatile VCID
Virtual Channel ID.
Definition DSIRegisters.h:101
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits
Definition DSIRegisters.h:511
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::PE3IE
uint32_t volatile PE3IE
PHY Error 3 Interrupt Enable.
Definition DSIRegisters.h:531
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE0IE
uint32_t volatile AE0IE
Acknowledge Error 0 Interrupt Enable.
Definition DSIRegisters.h:512
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE3IE
uint32_t volatile AE3IE
Acknowledge Error 3 Interrupt Enable.
Definition DSIRegisters.h:515
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE1IE
uint32_t volatile AE1IE
Acknowledge Error 1 Interrupt Enable.
Definition DSIRegisters.h:513
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE6IE
uint32_t volatile AE6IE
Acknowledge Error 6 Interrupt Enable.
Definition DSIRegisters.h:518
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::PE1IE
uint32_t volatile PE1IE
PHY Error 1 Interrupt Enable.
Definition DSIRegisters.h:529
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE14IE
uint32_t volatile AE14IE
Acknowledge Error 14 Interrupt Enable.
Definition DSIRegisters.h:526
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::PE0IE
uint32_t volatile PE0IE
PHY Error 0 Interrupt Enable.
Definition DSIRegisters.h:528
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE8IE
uint32_t volatile AE8IE
Acknowledge Error 8 Interrupt Enable.
Definition DSIRegisters.h:520
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::PE4IE
uint32_t volatile PE4IE
PHY Error 4 Interrupt Enable.
Definition DSIRegisters.h:532
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::volatile
uint32_t volatile
Definition DSIRegisters.h:533
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE5IE
uint32_t volatile AE5IE
Acknowledge Error 5 Interrupt Enable.
Definition DSIRegisters.h:517
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE2IE
uint32_t volatile AE2IE
Acknowledge Error 2 Interrupt Enable.
Definition DSIRegisters.h:514
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE13IE
uint32_t volatile AE13IE
Acknowledge Error 13 Interrupt Enable.
Definition DSIRegisters.h:525
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE4IE
uint32_t volatile AE4IE
Acknowledge Error 4 Interrupt Enable.
Definition DSIRegisters.h:516
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE15IE
uint32_t volatile AE15IE
Acknowledge Error 15 Interrupt Enable.
Definition DSIRegisters.h:527
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE11IE
uint32_t volatile AE11IE
Acknowledge Error 11 Interrupt Enable.
Definition DSIRegisters.h:523
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE10IE
uint32_t volatile AE10IE
Acknowledge Error 10 Interrupt Enable.
Definition DSIRegisters.h:522
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE9IE
uint32_t volatile AE9IE
Acknowledge Error 9 Interrupt Enable.
Definition DSIRegisters.h:521
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE12IE
uint32_t volatile AE12IE
Acknowledge Error 12 Interrupt Enable.
Definition DSIRegisters.h:524
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::PE2IE
uint32_t volatile PE2IE
PHY Error 2 Interrupt Enable.
Definition DSIRegisters.h:530
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Bits::AE7IE
uint32_t volatile AE7IE
Acknowledge Error 7 Interrupt Enable.
Definition DSIRegisters.h:519
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Fields
Definition DSIRegisters.h:535
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Fields::PEIE
uint32_t volatile PEIE
PHY Error 0-5 Interrupt Enable.
Definition DSIRegisters.h:537
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Fields::volatile
uint32_t volatile
Definition DSIRegisters.h:538
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::Fields::AEIE
uint32_t volatile AEIE
Acknowledge Error 0-15 Interrupt Enable.
Definition DSIRegisters.h:536
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields
Definition DSIRegisters.h:549
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::ECCSEIE
uint32_t volatile ECCSEIE
ECC Single-bit Error Interrupt Enable.
Definition DSIRegisters.h:552
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::GPTXEIE
uint32_t volatile GPTXEIE
Generic Payload Transmit Error Interrupt Enable.
Definition DSIRegisters.h:560
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::GPRDEIE
uint32_t volatile GPRDEIE
Generic Payload Read Error Interrupt Enable.
Definition DSIRegisters.h:561
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::CRCEIE
uint32_t volatile CRCEIE
CRC Error Interrupt Enable.
Definition DSIRegisters.h:554
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::TOLPRXIE
uint32_t volatile TOLPRXIE
Timeout Low-Power Reception Interrupt Enable.
Definition DSIRegisters.h:551
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::GPRXEIE
uint32_t volatile GPRXEIE
Generic Payload Receive Error Interrupt Enable.
Definition DSIRegisters.h:562
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::LPWREIE
uint32_t volatile LPWREIE
LTDC Payload Write Error Interrupt Enable.
Definition DSIRegisters.h:557
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::PSEIE
uint32_t volatile PSEIE
Packet Size Error Interrupt Enable.
Definition DSIRegisters.h:555
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::ECCMEIE
uint32_t volatile ECCMEIE
ECC Multi-bit Error Interrupt Enable.
Definition DSIRegisters.h:553
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::EOTPEIE
uint32_t volatile EOTPEIE
EoTp Error Interrupt Enable.
Definition DSIRegisters.h:556
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::volatile
uint32_t volatile
Definition DSIRegisters.h:563
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::TOHSTXIE
uint32_t volatile TOHSTXIE
Timeout High-Speed Transmission Interrupt Enable.
Definition DSIRegisters.h:550
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::GCWREIE
uint32_t volatile GCWREIE
Generic Command Write Error Interrupt Enable.
Definition DSIRegisters.h:558
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::Fields::GPWREIE
uint32_t volatile GPWREIE
Generic Payload Write Error Interrupt Enable.
Definition DSIRegisters.h:559
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits
Definition DSIRegisters.h:449
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE12
uint32_t volatile AE12
Acknowledge Error 12.
Definition DSIRegisters.h:462
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::volatile
uint32_t volatile
Definition DSIRegisters.h:471
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE6
uint32_t volatile AE6
Acknowledge Error 6.
Definition DSIRegisters.h:456
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE4
uint32_t volatile AE4
Acknowledge Error 4.
Definition DSIRegisters.h:454
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE2
uint32_t volatile AE2
Acknowledge Error 2.
Definition DSIRegisters.h:452
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE15
uint32_t volatile AE15
Acknowledge Error 15.
Definition DSIRegisters.h:465
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::PE4
uint32_t volatile PE4
PHY Error 4.
Definition DSIRegisters.h:470
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE10
uint32_t volatile AE10
Acknowledge Error 10.
Definition DSIRegisters.h:460
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE14
uint32_t volatile AE14
Acknowledge Error 14.
Definition DSIRegisters.h:464
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::PE2
uint32_t volatile PE2
PHY Error 2.
Definition DSIRegisters.h:468
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::PE3
uint32_t volatile PE3
PHY Error 3.
Definition DSIRegisters.h:469
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE13
uint32_t volatile AE13
Acknowledge Error 13.
Definition DSIRegisters.h:463
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::PE0
uint32_t volatile PE0
PHY Error 0.
Definition DSIRegisters.h:466
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE8
uint32_t volatile AE8
Acknowledge Error 8.
Definition DSIRegisters.h:458
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE1
uint32_t volatile AE1
Acknowledge Error 1.
Definition DSIRegisters.h:451
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE9
uint32_t volatile AE9
Acknowledge Error 9.
Definition DSIRegisters.h:459
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE5
uint32_t volatile AE5
Acknowledge Error 5.
Definition DSIRegisters.h:455
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE0
uint32_t volatile AE0
Acknowledge Error 0.
Definition DSIRegisters.h:450
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE7
uint32_t volatile AE7
Acknowledge Error 7.
Definition DSIRegisters.h:457
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE11
uint32_t volatile AE11
Acknowledge Error 11.
Definition DSIRegisters.h:461
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::AE3
uint32_t volatile AE3
Acknowledge Error 3.
Definition DSIRegisters.h:453
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Bits::PE1
uint32_t volatile PE1
PHY Error 1.
Definition DSIRegisters.h:467
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Fields
Definition DSIRegisters.h:473
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Fields::AE
uint32_t volatile AE
Acknowledge Error 0-15.
Definition DSIRegisters.h:474
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Fields::volatile
uint32_t volatile
Definition DSIRegisters.h:476
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::Fields::PE
uint32_t volatile PE
PHY Error 0-5.
Definition DSIRegisters.h:475
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits
Definition DSIRegisters.h:487
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::PSE
uint32_t volatile PSE
Packet Size Error.
Definition DSIRegisters.h:493
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::GCWRE
uint32_t volatile GCWRE
Generic Command Write Error.
Definition DSIRegisters.h:496
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::ECCME
uint32_t volatile ECCME
ECC Multi-bit Error.
Definition DSIRegisters.h:491
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::TOHSTX
uint32_t volatile TOHSTX
Timeout High-Speed Transmission.
Definition DSIRegisters.h:488
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::EOTPE
uint32_t volatile EOTPE
EoTp Error.
Definition DSIRegisters.h:494
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::ECCSE
uint32_t volatile ECCSE
ECC Single-bit Error.
Definition DSIRegisters.h:490
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::GPRXE
uint32_t volatile GPRXE
Generic Payload Receive Error.
Definition DSIRegisters.h:500
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::volatile
uint32_t volatile
Definition DSIRegisters.h:501
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::LPWRE
uint32_t volatile LPWRE
LTDC Payload Write Error.
Definition DSIRegisters.h:495
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::GPRDE
uint32_t volatile GPRDE
Generic Payload Read Error.
Definition DSIRegisters.h:499
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::GPTXE
uint32_t volatile GPTXE
Generic Payload Transmit Error.
Definition DSIRegisters.h:498
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::TOLPRX
uint32_t volatile TOLPRX
Timeout Low-Power Reception.
Definition DSIRegisters.h:489
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::CRCE
uint32_t volatile CRCE
CRC Error.
Definition DSIRegisters.h:492
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::Bits::GPWRE
uint32_t volatile GPWRE
Generic Payload Write Error.
Definition DSIRegisters.h:497
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCCCR
DSI Host LTDC Current Color Coding Register (DSI_LCCCR), chapter 20.15.49.
Definition DSIRegisters.h:638
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:640
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCCCR::COLC
imt::base::hal::stm32f769::peripherals::DSITypes::RgbColorCoding::Id volatile COLC
Color Coding.
Definition DSIRegisters.h:639
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCCCR::LPE
uint32_t volatile LPE
Loosely Packed Enable.
Definition DSIRegisters.h:641
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCCR
DSI Host LTDC Command Configuration Register (DSI_LCCR), chapter 20.15.22.
Definition DSIRegisters.h:218
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCCR::CMDSIZE
uint32_t volatile CMDSIZE
Command Size.
Definition DSIRegisters.h:219
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:220
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCOLCR
DSI Host LTDC Color Coding Register (DSI_LCOLCR), chapter 20.15.5.
Definition DSIRegisters.h:54
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCOLCR::volatile
uint32_t volatile
Definition DSIRegisters.h:56
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCOLCR::COLC
imt::base::hal::stm32f769::peripherals::DSITypes::RgbColorCoding::Id volatile COLC
Color Coding.
Definition DSIRegisters.h:55
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCOLCR::LPE
uint32_t volatile LPE
Loosly Packet Enable.
Definition DSIRegisters.h:57
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCVCIDR
DSI Host LTDC Current VCID Register (DSI_LCVCIDR), chapter 20.15.48.
Definition DSIRegisters.h:630
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCVCIDR::VCID
uint32_t volatile VCID
Virtual Channel ID.
Definition DSIRegisters.h:631
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LCVCIDR::volatile
uint32_t volatile
Definition DSIRegisters.h:632
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPCR
DSI Host LTDC Polarity Configuration Register (DSI_LPCR), chapter 20.15.6.
Definition DSIRegisters.h:64
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPCR::DEP
uint32_t volatile DEP
Data Enable Polarity.
Definition DSIRegisters.h:65
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPCR::volatile
uint32_t volatile
Definition DSIRegisters.h:68
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPCR::VSP
uint32_t volatile VSP
VSYNC Polarity.
Definition DSIRegisters.h:66
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPCR::HSP
uint32_t volatile HSP
HSYNC Polarity.
Definition DSIRegisters.h:67
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPMCCR
DSI Host Low-Power mode Current Configuration Register (DSI_LPMCCR), chapter 20.15....
Definition DSIRegisters.h:648
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPMCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:650
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPMCCR::VLPSIZE
uint32_t volatile VLPSIZE
VACT Largest Packet Size.
Definition DSIRegisters.h:649
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPMCCR::LPSIZE
uint32_t volatile LPSIZE
Largest Packet Size.
Definition DSIRegisters.h:651
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPMCR
DSI Host Low-Power mode Configuration Register (DSI_LPMCR), chapter 20.15.7.
Definition DSIRegisters.h:74
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPMCR::LPSIZE
uint32_t volatile LPSIZE
Largest Packet Size.
Definition DSIRegisters.h:77
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPMCR::volatile
uint32_t volatile
Definition DSIRegisters.h:76
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LPMCR::VLPSIZE
uint32_t volatile VLPSIZE
VACT Largest Packet Size.
Definition DSIRegisters.h:75
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LVCIDR
DSI Host LTDC VCID Register (DSI_LVCIDR), chapter 20.15.4.
Definition DSIRegisters.h:46
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LVCIDR::volatile
uint32_t volatile
Definition DSIRegisters.h:48
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_LVCIDR::VCID
uint32_t volatile VCID
Virtual Channel ID.
Definition DSIRegisters.h:47
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_MCR
DSI Host mode Configuration Register (DSI_MCR), chapter 20.15.10.
Definition DSIRegisters.h:108
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_MCR::volatile
uint32_t volatile
Definition DSIRegisters.h:110
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_MCR::CMDM
uint32_t volatile CMDM
Command Mode.
Definition DSIRegisters.h:109
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCONFR
DSI Host PHY Configuration Register (DSI_PCONFR), chapter 20.15.37.
Definition DSIRegisters.h:399
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCONFR::SW_TIME
uint32_t volatile SW_TIME
Stop Wait Time.
Definition DSIRegisters.h:402
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCONFR::NL
uint32_t volatile NL
Number of Lanes.
Definition DSIRegisters.h:400
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCONFR::volatile
uint32_t volatile
Definition DSIRegisters.h:401
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCR::Bits
Definition DSIRegisters.h:85
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCR::Bits::volatile
uint32_t volatile
Definition DSIRegisters.h:91
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCR::Bits::ECCRXE
uint32_t volatile ECCRXE
ECC Reception Enable.
Definition DSIRegisters.h:89
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCR::Bits::ETTXE
uint32_t volatile ETTXE
EoTp Transmission Enable.
Definition DSIRegisters.h:86
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCR::Bits::ETRXE
uint32_t volatile ETRXE
EoTp Reception Enable.
Definition DSIRegisters.h:87
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCR::Bits::BTAE
uint32_t volatile BTAE
Bus Turn Around Enable.
Definition DSIRegisters.h:88
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCR::Bits::CRCRXE
uint32_t volatile CRCRXE
CRC Reception Enable.
Definition DSIRegisters.h:90
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCTLR
DSI Host PHY Control Register (DSI_PCTLR), chapter 20.15.36.
Definition DSIRegisters.h:389
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCTLR::volatile
uint32_t volatile
Definition DSIRegisters.h:390
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCTLR::CKE
uint32_t volatile CKE
Clock Enable.
Definition DSIRegisters.h:392
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCTLR::DEN
uint32_t volatile DEN
Digital Enable.
Definition DSIRegisters.h:391
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PSR
DSI Host PHY Status Register (DSI_PSR), chapter 20.15.40.
Definition DSIRegisters.h:432
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PSR::volatile
uint32_t volatile
Definition DSIRegisters.h:433
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PSR::PSSC
uint32_t volatile PSSC
PHY Stop State Clock lane.
Definition DSIRegisters.h:435
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PSR::PSS1
uint32_t volatile PSS1
PHY Stop State lane 1.
Definition DSIRegisters.h:440
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PSR::PD
uint32_t volatile PD
PHY Direction.
Definition DSIRegisters.h:434
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PSR::UAN0
uint32_t volatile UAN0
ULPS Active Not lane 0.
Definition DSIRegisters.h:438
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PSR::RUE0
uint32_t volatile RUE0
RX ULPS Escape lane 0.
Definition DSIRegisters.h:439
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PSR::UAN1
uint32_t volatile UAN1
ULPS Active Not lane 1.
Definition DSIRegisters.h:441
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PSR::PSS0
uint32_t volatile PSS0
PHY Stop State lane 0.
Definition DSIRegisters.h:437
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PSR::UANC
uint32_t volatile UANC
ULPS Active Not Clock lane.
Definition DSIRegisters.h:436
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PTTCR
DSI Host PHY TX Triggers Configuration Register (DSI_PTTCR), chapter 20.15.39.
Definition DSIRegisters.h:424
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PTTCR::TX_TRIG
uint32_t volatile TX_TRIG
Transmission Trigger.
Definition DSIRegisters.h:425
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PTTCR::volatile
uint32_t volatile
Definition DSIRegisters.h:426
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PUCR::Bits
Definition DSIRegisters.h:410
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PUCR::Bits::UEDL
uint32_t volatile UEDL
ULPS Exit on Data Lane.
Definition DSIRegisters.h:414
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PUCR::Bits::URDL
uint32_t volatile URDL
ULPS Request on Data Lane.
Definition DSIRegisters.h:413
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PUCR::Bits::volatile
uint32_t volatile
Definition DSIRegisters.h:415
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PUCR::Bits::URCL
uint32_t volatile URCL
ULPS Request on Clock Lane.
Definition DSIRegisters.h:411
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PUCR::Bits::UECL
uint32_t volatile UECL
ULPS Exit on Clock Lane.
Definition DSIRegisters.h:412
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR0
DSI Host Timeout Counter Configuration Register 0 (DSI_TCCR0), chapter 20.15.27.
Definition DSIRegisters.h:297
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR0::HSTX_TOCNT
uint32_t volatile HSTX_TOCNT
High-Speed Transmission Timeout Counter.
Definition DSIRegisters.h:299
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR0::LPRX_TOCNT
uint32_t volatile LPRX_TOCNT
Low-power Reception Timeout Counter.
Definition DSIRegisters.h:298
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR1
DSI Host Timeout Counter Configuration Register 1 (DSI_TCCR1), chapter 20.15.28.
Definition DSIRegisters.h:305
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR1::HSRD_TOCNT
uint32_t volatile HSRD_TOCNT
High-Speed Read Timeout Counter.
Definition DSIRegisters.h:306
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR1::volatile
uint32_t volatile
Definition DSIRegisters.h:307
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR2
DSI Host Timeout Counter Configuration Register 2 (DSI_TCCR2), chapter 20.15.29.
Definition DSIRegisters.h:313
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR2::volatile
uint32_t volatile
Definition DSIRegisters.h:315
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR2::LPRD_TOCNT
uint32_t volatile LPRD_TOCNT
Low-Power Read Timeout Counter.
Definition DSIRegisters.h:314
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR3
DSI Host Timeout Counter Configuration Register 3 (DSI_TCCR3), chapter 20.15.30.
Definition DSIRegisters.h:321
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR3::volatile
uint32_t volatile
Definition DSIRegisters.h:323
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR3::HSWR_TOCNT
uint32_t volatile HSWR_TOCNT
High-Speed Write Timeout Counter.
Definition DSIRegisters.h:322
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR3::PM
uint32_t volatile PM
Presp Mode.
Definition DSIRegisters.h:324
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR4
DSI Host Timeout Counter Configuration Register 4 (DSI_TCCR4), chapter 20.15.31.
Definition DSIRegisters.h:331
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR4::LPWR_TOCNT
uint32_t volatile LPWR_TOCNT
Low-Power Write Timeout Counter.
Definition DSIRegisters.h:332
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR4::volatile
uint32_t volatile
Definition DSIRegisters.h:333
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR5
DSI Host Timeout Counter Configuration Register 5 (DSI_TCCR5), chapter 20.15.32.
Definition DSIRegisters.h:339
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR5::volatile
uint32_t volatile
Definition DSIRegisters.h:341
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TCCR5::BTA_TOCNT
uint32_t volatile BTA_TOCNT
Bus-Turn-Around Timeout Counter.
Definition DSIRegisters.h:340
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCCR
DSI Host Register (DSI_TDCCR), not documented in TRM Rev4, information from QubeMx Example HAL.
Definition DSIRegisters.h:754
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCCR::SVS
uint32_t volatile SVS
Second VSYNC.
Definition DSIRegisters.h:757
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCCR::THREE3DF
uint32_t volatile THREE3DF
3D Format
Definition DSIRegisters.h:756
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCCR::THREEDM
uint32_t volatile THREEDM
3D Mode
Definition DSIRegisters.h:755
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCCR::S3DC
uint32_t volatile S3DC
Send 3D Control.
Definition DSIRegisters.h:760
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:759
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCCR::RF
uint32_t volatile RF
Right First.
Definition DSIRegisters.h:758
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCR
DSI Host Register DSI_TDCR), not documented in TRM Rev4, information from QubeMx Example HAL.
Definition DSIRegisters.h:347
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCR::THREE3DF
uint32_t volatile THREE3DF
3D Format
Definition DSIRegisters.h:349
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCR::THREEDM
uint32_t volatile THREEDM
3D Mode
Definition DSIRegisters.h:348
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCR::RF
uint32_t volatile RF
Right First.
Definition DSIRegisters.h:351
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCR::SVS
uint32_t volatile SVS
Second VSYNC.
Definition DSIRegisters.h:350
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCR::volatile
uint32_t volatile
Definition DSIRegisters.h:352
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_TDCR::S3DC
uint32_t volatile S3DC
Send 3D Control.
Definition DSIRegisters.h:353
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VCCCR
DSI Host Video Chunks Current Configuration Register (DSI_VCCCR), chapter 20.15.53.
Definition DSIRegisters.h:682
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VCCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:684
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VCCCR::NUMC
uint32_t volatile NUMC
Number of Chunks.
Definition DSIRegisters.h:683
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VCCR
DSI Host Video Chunks Configuration Register (DSI_VCCR), chapter 20.15.13.
Definition DSIRegisters.h:146
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:148
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VCCR::NUMC
uint32_t volatile NUMC
Number of Chunks.
Definition DSIRegisters.h:147
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VHBPCCR
DSI Host Video HBP Current Configuration Register (DSI_VHBPCCR), chapter 20.15.56.
Definition DSIRegisters.h:706
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VHBPCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:708
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VHBPCCR::HBP
uint32_t volatile HBP
Horizontal Back-Porch duration.
Definition DSIRegisters.h:707
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VHBPCR
DSI Host Video HBP Configuration Register (DSI_VHBPCR), chapter 20.15.16.
Definition DSIRegisters.h:170
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VHBPCR::HBP
uint32_t volatile HBP
Horizontal Back-Porch duration.
Definition DSIRegisters.h:171
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VHBPCR::volatile
uint32_t volatile
Definition DSIRegisters.h:172
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VHSACCR
DSI Host Video HSA Current Configuration Register (DSI_VHSACCR), chapter 20.15.55.
Definition DSIRegisters.h:698
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VHSACCR::volatile
uint32_t volatile
Definition DSIRegisters.h:700
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VHSACCR::HSA
uint32_t volatile HSA
Horizontal Synchronism Active duration.
Definition DSIRegisters.h:699
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VHSACR
DSI Host Video HSA Configuration Register (DSI_VHSACR), chapter 20.15.15.
Definition DSIRegisters.h:162
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VHSACR::volatile
uint32_t volatile
Definition DSIRegisters.h:164
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VHSACR::HSA
uint32_t volatile HSA
Horizontal Synchronism Active duration.
Definition DSIRegisters.h:163
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VLCCR
DSI Host Video Line Current Configuration Register (DSI_VLCCR), chapter 20.15.57.
Definition DSIRegisters.h:714
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VLCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:716
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VLCCR::HLINE
uint32_t volatile HLINE
Horizontal Line duration.
Definition DSIRegisters.h:715
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VLCR
DSI Host Video Line Configuration Register (DSI_VLCR), chapter 20.15.17.
Definition DSIRegisters.h:178
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VLCR::HLINE
uint32_t volatile HLINE
Horizontal Line duration.
Definition DSIRegisters.h:179
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VLCR::volatile
uint32_t volatile
Definition DSIRegisters.h:180
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCCR
DSI Host Video mode Current Configuration Register (DSI_VMCCR), chapter 20.15.51.
Definition DSIRegisters.h:658
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:668
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCCR::LPHBPE
uint32_t volatile LPHBPE
Low-power Horizontal Back-porch Enable.
Definition DSIRegisters.h:664
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCCR::FBTAAE
uint32_t volatile FBTAAE
Frame BTA Acknowledge Enable.
Definition DSIRegisters.h:666
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCCR::LPVAE
uint32_t volatile LPVAE
Low-power Vertical Active Enable.
Definition DSIRegisters.h:663
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCCR::LPVSAE
uint32_t volatile LPVSAE
Low-power Vertical Sync time Enable.
Definition DSIRegisters.h:660
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCCR::LPCE
uint32_t volatile LPCE
Low-power Command Enable.
Definition DSIRegisters.h:667
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCCR::LPHFE
uint32_t volatile LPHFE
Low-power Horizontal Front-porch Enable.
Definition DSIRegisters.h:665
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCCR::LPVBPE
uint32_t volatile LPVBPE
Low-power Vertical Back-porch Enable.
Definition DSIRegisters.h:661
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCCR::LPVFPE
uint32_t volatile LPVFPE
Low-power Vertical Front-porch Enable.
Definition DSIRegisters.h:662
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCCR::VMT
uint32_t volatile VMT
Video Mode Type.
Definition DSIRegisters.h:659
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR
DSI Host Video mode Configuration Register (DSI_VMCR), chapter 20.15.11.
Definition DSIRegisters.h:116
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::LPVBPE
uint32_t volatile LPVBPE
Low-power Vertical Back-Porch Enable.
Definition DSIRegisters.h:120
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::LPVAE
uint32_t volatile LPVAE
Low-Power Vertical Active Enable.
Definition DSIRegisters.h:122
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::volatile
uint32_t volatile
Definition DSIRegisters.h:118
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::LPHBPE
uint32_t volatile LPHBPE
Low-Power Horizontal Back-Porch Enable.
Definition DSIRegisters.h:123
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::LPVFPE
uint32_t volatile LPVFPE
Low-power Vertical Front-porch Enable.
Definition DSIRegisters.h:121
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::PGM
uint32_t volatile PGM
Pattern Generator Mode.
Definition DSIRegisters.h:129
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::LPHFPE
uint32_t volatile LPHFPE
Low-Power Horizontal Front-Porch Enable.
Definition DSIRegisters.h:124
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::VMT
uint32_t volatile VMT
Video Mode Type.
Definition DSIRegisters.h:117
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::PGO
uint32_t volatile PGO
Pattern Generator Orientation.
Definition DSIRegisters.h:131
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::LPCE
uint32_t volatile LPCE
Low-Power Command Enable.
Definition DSIRegisters.h:126
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::FBTAAE
uint32_t volatile FBTAAE
Frame Bus-Turn-Around Acknowledge Enable.
Definition DSIRegisters.h:125
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::LPVSAE
uint32_t volatile LPVSAE
Low-Power Vertical Sync Active Enable.
Definition DSIRegisters.h:119
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VMCR::PGE
uint32_t volatile PGE
Pattern Generator Enable.
Definition DSIRegisters.h:127
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VNPCCR
DSI Host Video Null Packet Current Configuration Register (DSI_VNPCCR), chapter 20....
Definition DSIRegisters.h:690
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VNPCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:692
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VNPCCR::NPSIZE
uint32_t volatile NPSIZE
Null Packet Size.
Definition DSIRegisters.h:691
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VNPCR
DSI Host Video Null Packet Configuration Register (DSI_VNPCR), chapter 20.15.14.
Definition DSIRegisters.h:154
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VNPCR::volatile
uint32_t volatile
Definition DSIRegisters.h:156
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VNPCR::NPSIZE
uint32_t volatile NPSIZE
Null Packet Size.
Definition DSIRegisters.h:155
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VPCCR
DSI Host Video Packet Current Configuration Register (DSI_VPCCR), chapter 20.15.52.
Definition DSIRegisters.h:674
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VPCCR::VPSIZE
uint32_t volatile VPSIZE
Video Packet Size.
Definition DSIRegisters.h:675
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VPCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:676
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VPCR
DSI Host Video Packet Configuration Register (DSI_VPCR), chapter 20.15.12.
Definition DSIRegisters.h:138
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VPCR::volatile
uint32_t volatile
Definition DSIRegisters.h:140
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VPCR::VPSIZE
uint32_t volatile VPSIZE
Video Packet Size.
Definition DSIRegisters.h:139
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VSCR
DSI Host Video Shadow Control Register (DSI_VSCR), chapter 20.15.47.
Definition DSIRegisters.h:620
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VSCR::volatile
uint32_t volatile
Definition DSIRegisters.h:622
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VSCR::UR
uint32_t volatile UR
Update Register.
Definition DSIRegisters.h:623
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VSCR::EN
uint32_t volatile EN
Enable.
Definition DSIRegisters.h:621
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVACCR
DSI Host Video VA Current Configuration Register (DSI_VVACCR), chapter 20.15.61.
Definition DSIRegisters.h:746
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVACCR::volatile
uint32_t volatile
Definition DSIRegisters.h:748
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVACCR::VA
uint32_t volatile VA
Vertical active duration.
Definition DSIRegisters.h:747
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVACR
DSI Host Video VA Configuration Register (DSI_VVACR), chapter 20.15.21.
Definition DSIRegisters.h:210
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVACR::VA
uint32_t volatile VA
Vertical Active duration.
Definition DSIRegisters.h:211
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVACR::volatile
uint32_t volatile
Definition DSIRegisters.h:212
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVBPCCR
DSI Host Video VBP Current Configuration Register (DSI_VVBPCCR), chapter 20.15.59.
Definition DSIRegisters.h:730
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVBPCCR::VBP
uint32_t volatile VBP
Vertical Back-Porch duration.
Definition DSIRegisters.h:731
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVBPCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:732
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVBPCR
DSI Host Video VBP Configuration Register (DSI_VVBPCR), chapter 20.15.19.
Definition DSIRegisters.h:194
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVBPCR::volatile
uint32_t volatile
Definition DSIRegisters.h:196
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVBPCR::VBP
uint32_t volatile VBP
Vertical Back-Porch duration.
Definition DSIRegisters.h:195
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVFPCCR
DSI Host Video VFP Current Configuration Register (DSI_VVFPCCR), chapter 20.15.60.
Definition DSIRegisters.h:738
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVFPCCR::volatile
uint32_t volatile
Definition DSIRegisters.h:740
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVFPCCR::VFP
uint32_t volatile VFP
Vertical Front-Porch duration.
Definition DSIRegisters.h:739
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVFPCR
DSI Host Video VFP Configuration Register (DSI_VVFPCR), chapter 20.15.20.
Definition DSIRegisters.h:202
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVFPCR::VFP
uint32_t volatile VFP
Vertical Front-Porch duration.
Definition DSIRegisters.h:203
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVFPCR::volatile
uint32_t volatile
Definition DSIRegisters.h:204
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVSACCR
DSI Host Video VSA Current Configuration Register (DSI_VVSACCR), chapter 20.15.58.
Definition DSIRegisters.h:722
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVSACCR::volatile
uint32_t volatile
Definition DSIRegisters.h:724
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVSACCR::VSA
uint32_t volatile VSA
Vertical Synchronism Active duration.
Definition DSIRegisters.h:723
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVSACR
DSI Host Video VSA Configuration Register (DSI_VVSACR), chapter 20.15.18.
Definition DSIRegisters.h:186
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVSACR::volatile
uint32_t volatile
Definition DSIRegisters.h:188
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_VVSACR::VSA
uint32_t volatile VSA
Vertical Synchronism Active duration.
Definition DSIRegisters.h:187
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCFGR
20.16 DSI Wrapper Registers
Definition DSIRegisters.h:771
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCFGR::VSPOL
uint32_t volatile VSPOL
VSync Polarity.
Definition DSIRegisters.h:777
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCFGR::COLMUX
imt::base::hal::stm32f769::peripherals::DSITypes::RgbColorCoding::Id volatile COLMUX
Color Multiplexing.
Definition DSIRegisters.h:773
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCFGR::AR
uint32_t volatile AR
Automatic Refresh.
Definition DSIRegisters.h:776
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCFGR::TEPOL
uint32_t volatile TEPOL
Tearing Effect Polarity.
Definition DSIRegisters.h:775
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCFGR::DSIM
uint32_t volatile DSIM
DSI Mode.
Definition DSIRegisters.h:772
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCFGR::TESRC
uint32_t volatile TESRC
Tearing Effect Source.
Definition DSIRegisters.h:774
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCFGR::volatile
uint32_t volatile
Definition DSIRegisters.h:778
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCR
DSI Wrapper Control Register (DSI_WCR), chapter 20.16.2.
Definition DSIRegisters.h:784
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCR::SHTDN
uint32_t volatile SHTDN
Shutdown.
Definition DSIRegisters.h:786
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCR::COLM
uint32_t volatile COLM
Color Mode.
Definition DSIRegisters.h:785
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCR::DSIEN
uint32_t volatile DSIEN
DSI Enable.
Definition DSIRegisters.h:788
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCR::LTDCEN
uint32_t volatile LTDCEN
LTDC Enable.
Definition DSIRegisters.h:787
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WCR::volatile
uint32_t volatile
Definition DSIRegisters.h:789
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIER
DSI Wrapper Interrupt Enable Register (DSI_WIER), chapter 20.16.3.
Definition DSIRegisters.h:795
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIER::PLLL
uint32_t volatile PLLL
PLL Lock Interrupt Enable.
Definition DSIRegisters.h:799
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIER::RR
uint32_t volatile RR
Regulator Ready Interrupt Enable.
Definition DSIRegisters.h:802
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIER::TE
uint32_t volatile TE
Tearing Effect Interrupt Enable.
Definition DSIRegisters.h:796
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIER::PLLU
uint32_t volatile PLLU
PLL Unlock Interrupt Enable.
Definition DSIRegisters.h:800
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIER::ER
uint32_t volatile ER
End of Refresh Interrupt Enable.
Definition DSIRegisters.h:797
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIER::volatile
uint32_t volatile
Definition DSIRegisters.h:798
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIFCR
DSI Wrapper Interrupt Flag Clear Register (DSI_WIFCR), chapter 20.16.5.
Definition DSIRegisters.h:826
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIFCR::RR
uint32_t volatile RR
Clear Regulator Ready Interrupt Flag.
Definition DSIRegisters.h:833
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIFCR::TE
uint32_t volatile TE
Clear Tearing Effect Interrupt Flag.
Definition DSIRegisters.h:827
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIFCR::ER
uint32_t volatile ER
Clear End of Refresh Interrupt Flag.
Definition DSIRegisters.h:828
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIFCR::PLLL
uint32_t volatile PLLL
Clear PLL Lock Interrupt Flag.
Definition DSIRegisters.h:830
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIFCR::PLLU
uint32_t volatile PLLU
Clear PLL Unlock Interrupt Flag.
Definition DSIRegisters.h:831
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WIFCR::volatile
uint32_t volatile
Definition DSIRegisters.h:829
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WISR
DSI Wrapper Interrupt & Status Register (DSI_WISR), chapter 20.16.4.
Definition DSIRegisters.h:809
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WISR::PLLLS
uint32_t volatile PLLLS
PLL Lock Status.
Definition DSIRegisters.h:814
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WISR::RRS
uint32_t volatile RRS
Regulator Ready Status.
Definition DSIRegisters.h:818
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WISR::PLLL
uint32_t volatile PLLL
PLL Lock Interrupt Flag.
Definition DSIRegisters.h:815
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WISR::TE
uint32_t volatile TE
Tearing Effect Interrupt Flag.
Definition DSIRegisters.h:810
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WISR::BUSY
uint32_t volatile BUSY
Busy Flag.
Definition DSIRegisters.h:812
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WISR::volatile
uint32_t volatile
Definition DSIRegisters.h:813
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WISR::ER
uint32_t volatile ER
End of Refresh Interrupt Flag.
Definition DSIRegisters.h:811
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WISR::PLLU
uint32_t volatile PLLU
PLL Unlock Interrupt Flag.
Definition DSIRegisters.h:816
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WISR::RR
uint32_t volatile RR
Regulator Ready Interrupt Flag.
Definition DSIRegisters.h:819
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0
DSI Wrapper PHY Configuration Register 0 (DSI_WPCR0), chapter 20.16.6.
Definition DSIRegisters.h:840
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::SWCL
FunctionalState::Id volatile SWCL
Swap pins on clock lane.
Definition DSIRegisters.h:842
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::HSIDL0
uint32_t volatile HSIDL0
Invert the high-speed data signal on data lane 0.
Definition DSIRegisters.h:846
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::SWDL0
uint32_t volatile SWDL0
Swap pins on data lane 0.
Definition DSIRegisters.h:843
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::TLPXDEN
uint32_t volatile TLPXDEN
Custom Time for t-LPX for data lanes Enable.
Definition DSIRegisters.h:860
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::HSICL
uint32_t volatile HSICL
Invert the high-speed data signal on clock lane.
Definition DSIRegisters.h:845
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::TCLKPOSTEN
uint32_t volatile TCLKPOSTEN
Custom Time for t-CLKPOST Enable.
Definition DSIRegisters.h:863
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::HSIDL1
uint32_t volatile HSIDL1
Invert the high-speed data signal on data lane 1.
Definition DSIRegisters.h:847
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::TDDL
uint32_t volatile TDDL
Turn Disable Data Lanes.
Definition DSIRegisters.h:852
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::PDEN
uint32_t volatile PDEN
Pull-Down Enable.
Definition DSIRegisters.h:854
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::FTXSMDL
uint32_t volatile FTXSMDL
Force data lanes in TX stop mode.
Definition DSIRegisters.h:849
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::THSEXITEN
uint32_t volatile THSEXITEN
Custom Time for t-HSEXIT Enable.
Definition DSIRegisters.h:861
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::FTXSMCL
uint32_t volatile FTXSMCL
Force clock lane in TX stop mode.
Definition DSIRegisters.h:848
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::TLPXCEN
uint32_t volatile TLPXCEN
Custom Time for t-LPX for clock lane Enable.
Definition DSIRegisters.h:862
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::CDOFFDL
uint32_t volatile CDOFFDL
Contention detection OFF on data lines.
Definition DSIRegisters.h:850
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::TCLKPREPEN
uint32_t volatile TCLKPREPEN
Custom Time for t-CLKPREPARE Enable.
Definition DSIRegisters.h:855
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::THSPREPEN
uint32_t volatile THSPREPEN
Custom Time for t-HSPREPARE Enable.
Definition DSIRegisters.h:857
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::SWDL1
uint32_t volatile SWDL1
Swap pins on data lane 1.
Definition DSIRegisters.h:844
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::THSZEROEN
uint32_t volatile THSZEROEN
Custom Time for t-HSZERO Enable.
Definition DSIRegisters.h:859
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::THSTRAILEN
uint32_t volatile THSTRAILEN
Custom Time for t-HSTRAIL Enable.
Definition DSIRegisters.h:858
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::UIX4
uint32_t volatile UIX4
Unit Interval multiplied by 4.
Definition DSIRegisters.h:841
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::TCLKZEROEN
uint32_t volatile TCLKZEROEN
Custom Time for t-CLKZERO Enable.
Definition DSIRegisters.h:856
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR0::volatile
uint32_t volatile
Definition DSIRegisters.h:851
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1
DSI Wrapper PHY Configuration Register 1 (DSI_WPCR1), chapter 20.16.7.
Definition DSIRegisters.h:870
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::volatile
uint32_t volatile
Definition DSIRegisters.h:873
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::FLPRXLPM
uint32_t volatile FLPRXLPM
Forces LP Receiver in Low-Power Mode.
Definition DSIRegisters.h:883
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::LPSRCDL
uint32_t volatile LPSRCDL
Low-Power transmission Slew Rate Compensation on Data Lanes.
Definition DSIRegisters.h:875
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::HSTXDDL
uint32_t volatile HSTXDDL
High-Speed Transmission Delay on Data Lanes.
Definition DSIRegisters.h:872
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::SDDC
uint32_t volatile SDDC
SDD Control.
Definition DSIRegisters.h:877
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::HSTXDCL
uint32_t volatile HSTXDCL
High-Speed Transmission Delay on Clock Lane.
Definition DSIRegisters.h:871
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::HSTXSRCDL
uint32_t volatile HSTXSRCDL
High-Speed Transmission slew-rate control on Data Lanes.
Definition DSIRegisters.h:881
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::LPRXVCDL
uint32_t volatile LPRXVCDL
Low-Power Reception V-IL Compensation on Data Lanes: information from QubeMx Example HAL.
Definition DSIRegisters.h:879
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::HSTXSRCCL
uint32_t volatile HSTXSRCCL
High-Speed Transmission slew-rate control on Clock Lane.
Definition DSIRegisters.h:880
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::LPSRCCL
uint32_t volatile LPSRCCL
Low-Power transmission Slew Rate Compensation on Clock Lane.
Definition DSIRegisters.h:874
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::LPRXFT
uint32_t volatile LPRXFT
Low-Power RX low-pass Filtering Tuning.
Definition DSIRegisters.h:885
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR2
DSI Wrapper PHY Configuration Register 2 (DSI_WPCR2), chapter 20.16.8.
Definition DSIRegisters.h:892
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR2::THSPREP
uint32_t volatile THSPREP
t-HSPREPARE
Definition DSIRegisters.h:895
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR2::THSTRAIL
uint32_t volatile THSTRAIL
t-HSTRAIL
Definition DSIRegisters.h:896
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR2::TCLKPREP
uint32_t volatile TCLKPREP
t-CLKPREPARE
Definition DSIRegisters.h:893
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR2::TCLKZERO
uint32_t volatile TCLKZERO
t-CLKZERO
Definition DSIRegisters.h:894
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR3
DSI Wrapper PHY Configuration Register 3 (DSI_WPCR3), chapter 20.16.9.
Definition DSIRegisters.h:902
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR3::TLPXD
uint32_t volatile TLPXD
t-LPX for data lanes
Definition DSIRegisters.h:904
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR3::TLPXC
uint32_t volatile TLPXC
t-LPX for clock lane
Definition DSIRegisters.h:906
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR3::THSZERO
uint32_t volatile THSZERO
t-HSZERO
Definition DSIRegisters.h:903
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR3::THSEXIT
uint32_t volatile THSEXIT
t-HSEXIT
Definition DSIRegisters.h:905
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR4
DSI Wrapper PHY Configuration Register 4 (DSI_WPCR4), chapter 20.16.10.
Definition DSIRegisters.h:912
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR4::TCLKPOST
uint32_t volatile TCLKPOST
t-CLKPOST
Definition DSIRegisters.h:913
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR4::volatile
uint32_t volatile
Definition DSIRegisters.h:914
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WRPCR
DSI Wrapper Regulator and PLL Control Register (DSI_WRPCR), chapter 20.16.11.
Definition DSIRegisters.h:920
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WRPCR::PLLEN
uint32_t volatile PLLEN
PLL Enable.
Definition DSIRegisters.h:921
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WRPCR::NDIV
uint32_t volatile NDIV
PLL Loop Division Factor.
Definition DSIRegisters.h:923
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WRPCR::volatile
uint32_t volatile
Definition DSIRegisters.h:922
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WRPCR::REGEN
uint32_t volatile REGEN
Regulator Enable.
Definition DSIRegisters.h:929
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WRPCR::IDF
uint32_t volatile IDF
PLL Input Division Factor.
Definition DSIRegisters.h:925
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WRPCR::ODF
uint32_t volatile ODF
PLL Output Division Factor.
Definition DSIRegisters.h:927
imt::base::hal::stm32f769::registers::DSIRegisters
DSI host controller (DSI) module register structure.
Definition DSIRegisters.h:22
imt::base::hal::stm32f769::registers::DSIRegisters::LCCR
volatile DSI_LCCR LCCR
DSI Host LTDC Command Configuration Register, Address offset: 0x64.
Definition DSIRegisters.h:963
imt::base::hal::stm32f769::registers::DSIRegisters::PUCR
volatile DSI_PUCR PUCR
DSI Host PHY ULPS Control Register, Address offset: 0xA8.
Definition DSIRegisters.h:980
imt::base::hal::stm32f769::registers::DSIRegisters::VVFPCR
volatile DSI_VVFPCR VVFPCR
DSI Host Video VFP Configuration Register, Address offset: 0x5C.
Definition DSIRegisters.h:961
imt::base::hal::stm32f769::registers::DSIRegisters::MCR
volatile DSI_MCR MCR
DSI Host Mode Configuration Register, Address offset: 0x34.
Definition DSIRegisters.h:951
imt::base::hal::stm32f769::registers::DSIRegisters::reserved2
uint32_t volatile reserved2[3]
Reserved, 0xD0 - 0xD7.
Definition DSIRegisters.h:988
imt::base::hal::stm32f769::registers::DSIRegisters::TCCR1
volatile DSI_TCCR1 TCCR1
DSI Host Timeout Counter Configuration Register 1, Address offset: 0x7C.
Definition DSIRegisters.h:969
imt::base::hal::stm32f769::registers::DSIRegisters::PCTLR
volatile DSI_PCTLR PCTLR
DSI Host PHY Control Register, Address offset: 0xA0.
Definition DSIRegisters.h:978
imt::base::hal::stm32f769::registers::DSIRegisters::VR
uint32_t volatile VR
DSI Host Version Register, Address offset: 0x00.
Definition DSIRegisters.h:941
imt::base::hal::stm32f769::registers::DSIRegisters::FIR0
volatile DSI_FIR0 FIR0
DSI Host Force Interrupt Register 0, Address offset: 0xD8.
Definition DSIRegisters.h:989
imt::base::hal::stm32f769::registers::DSIRegisters::TCCR2
volatile DSI_TCCR2 TCCR2
DSI Host Timeout Counter Configuration Register 2, Address offset: 0x80.
Definition DSIRegisters.h:970
imt::base::hal::stm32f769::registers::DSIRegisters::VNPCR
volatile DSI_VNPCR VNPCR
DSI Host Video Null Packet Configuration Register, Address offset: 0x44.
Definition DSIRegisters.h:955
imt::base::hal::stm32f769::registers::DSIRegisters::VVFPCCR
volatile DSI_VVFPCCR VVFPCCR
DSI Host Video VFP Current Configuration Register, Address offset: 0x15C.
Definition DSIRegisters.h:1008
imt::base::hal::stm32f769::registers::DSIRegisters::WPCR1
volatile DSI_WPCR1 WPCR1
DSI Wrapper PHY Configuration Register 1, Address offset: 0x41C.
Definition DSIRegisters.h:1020
imt::base::hal::stm32f769::registers::DSIRegisters::reserved7
uint32_t volatile reserved7[11]
Reserved, 0x164 - 0x18F.
Definition DSIRegisters.h:1010
imt::base::hal::stm32f769::registers::DSIRegisters::PCR
volatile DSI_PCR PCR
DSI Host Protocol Configuration Register, Address offset: 0x2C.
Definition DSIRegisters.h:949
imt::base::hal::stm32f769::registers::DSIRegisters::WCR
volatile DSI_WCR WCR
DSI Wrapper Control Register, Address offset: 0x404.
Definition DSIRegisters.h:1014
imt::base::hal::stm32f769::registers::DSIRegisters::CLTCR
volatile DSI_CLTCR CLTCR
DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98.
Definition DSIRegisters.h:976
imt::base::hal::stm32f769::registers::DSIRegisters::VHBPCCR
volatile DSI_VHBPCCR VHBPCCR
DSI Host Video HBP Current Configuration Register, Address offset: 0x14C.
Definition DSIRegisters.h:1004
imt::base::hal::stm32f769::registers::DSIRegisters::FIR1
volatile DSI_FIR1 FIR1
DSI Host Force Interrupt Register 1, Address offset: 0xDC.
Definition DSIRegisters.h:990
imt::base::hal::stm32f769::registers::DSIRegisters::VVBPCCR
volatile DSI_VVBPCCR VVBPCCR
DSI Host Video VBP Current Configuration Register, Address offset: 0x158.
Definition DSIRegisters.h:1007
imt::base::hal::stm32f769::registers::DSIRegisters::reserved8
uint32_t volatile reserved8[155]
Reserved, 0x194 - 0x3FF.
Definition DSIRegisters.h:1012
imt::base::hal::stm32f769::registers::DSIRegisters::WPCR4
volatile DSI_WPCR4 WPCR4
DSI Wrapper PHY Configuration Register 4, Address offset: 0x428.
Definition DSIRegisters.h:1023
imt::base::hal::stm32f769::registers::DSIRegisters::IER1
volatile DSI_IER1 IER1
DSI Host Interrupt Enable Register 1, Address offset: 0xC8.
Definition DSIRegisters.h:987
imt::base::hal::stm32f769::registers::DSIRegisters::LPCR
volatile DSI_LPCR LPCR
DSI Host LTDC Polarity Configuration Register, Address offset: 0x14.
Definition DSIRegisters.h:946
imt::base::hal::stm32f769::registers::DSIRegisters::reserved10
uint32_t volatile reserved10
Reserved, 0x42C.
Definition DSIRegisters.h:1024
imt::base::hal::stm32f769::registers::DSIRegisters::VVACR
volatile DSI_VVACR VVACR
DSI Host Video VA Configuration Register, Address offset: 0x60.
Definition DSIRegisters.h:962
imt::base::hal::stm32f769::registers::DSIRegisters::VCCCR
volatile DSI_VCCCR VCCCR
DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140.
Definition DSIRegisters.h:1001
imt::base::hal::stm32f769::registers::DSIRegisters::PTTCR
volatile DSI_PTTCR PTTCR
DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC.
Definition DSIRegisters.h:981
imt::base::hal::stm32f769::registers::DSIRegisters::VVBPCR
volatile DSI_VVBPCR VVBPCR
DSI Host Video VBP Configuration Register, Address offset: 0x58.
Definition DSIRegisters.h:960
imt::base::hal::stm32f769::registers::DSIRegisters::TCCR5
volatile DSI_TCCR5 TCCR5
DSI Host Timeout Counter Configuration Register 5, Address offset: 0x8C.
Definition DSIRegisters.h:973
imt::base::hal::stm32f769::registers::DSIRegisters::VMCCR
volatile DSI_VMCCR VMCCR
DSI Host Video Mode Current Configuration Register, Address offset: 0x138.
Definition DSIRegisters.h:999
imt::base::hal::stm32f769::registers::DSIRegisters::VPCR
volatile DSI_VPCR VPCR
DSI Host Video Packet Configuration Register, Address offset: 0x3C.
Definition DSIRegisters.h:953
imt::base::hal::stm32f769::registers::DSIRegisters::WPCR0
volatile DSI_WPCR0 WPCR0
DSI Wrapper PHY Configuration Register 0, Address offset: 0x418.
Definition DSIRegisters.h:1019
imt::base::hal::stm32f769::registers::DSIRegisters::TCCR3
volatile DSI_TCCR3 TCCR3
DSI Host Timeout Counter Configuration Register 3, Address offset: 0x84.
Definition DSIRegisters.h:971
imt::base::hal::stm32f769::registers::DSIRegisters::TCCR0
volatile DSI_TCCR0 TCCR0
DSI Host Timeout Counter Configuration Register 0, Address offset: 0x78.
Definition DSIRegisters.h:968
imt::base::hal::stm32f769::registers::DSIRegisters::GHCR
volatile DSI_GHCR GHCR
DSI Host Generic Header Configuration Register, Address offset: 0x6C.
Definition DSIRegisters.h:965
imt::base::hal::stm32f769::registers::DSIRegisters::VSCR
volatile DSI_VSCR VSCR
DSI Host Video Shadow Control Register, Address offset: 0x100.
Definition DSIRegisters.h:992
imt::base::hal::stm32f769::registers::DSIRegisters::LCVCIDR
volatile DSI_LCVCIDR LCVCIDR
DSI Host LTDC Current VCID Register, Address offset: 0x10C.
Definition DSIRegisters.h:994
imt::base::hal::stm32f769::registers::DSIRegisters::VHBPCR
volatile DSI_VHBPCR VHBPCR
DSI Host Video HBP Configuration Register, Address offset: 0x4C.
Definition DSIRegisters.h:957
imt::base::hal::stm32f769::registers::DSIRegisters::VVSACCR
volatile DSI_VVSACCR VVSACCR
DSI Host Video VSA Current Configuration Register, Address offset: 0x154.
Definition DSIRegisters.h:1006
imt::base::hal::stm32f769::registers::DSIRegisters::reserved4
uint32_t volatile reserved4[2]
Reserved, 0x104 - 0x10B.
Definition DSIRegisters.h:993
imt::base::hal::stm32f769::registers::DSIRegisters::WPCR2
volatile DSI_WPCR2 WPCR2
DSI Wrapper PHY Configuration Register 2, Address offset: 0x420.
Definition DSIRegisters.h:1021
imt::base::hal::stm32f769::registers::DSIRegisters::VHSACR
volatile DSI_VHSACR VHSACR
DSI Host Video HSA Configuration Register, Address offset: 0x48.
Definition DSIRegisters.h:956
imt::base::hal::stm32f769::registers::DSIRegisters::CR
volatile DSI_CR CR
DSI Host Control Register, Address offset: 0x04.
Definition DSIRegisters.h:942
imt::base::hal::stm32f769::registers::DSIRegisters::WCFGR
volatile DSI_WCFGR WCFGR
DSI Wrapper Configuration Register, Address offset: 0x400.
Definition DSIRegisters.h:1013
imt::base::hal::stm32f769::registers::DSIRegisters::LPMCR
volatile DSI_LPMCR LPMCR
DSI Host Low-Power Mode Configuration Register, Address offset: 0x18.
Definition DSIRegisters.h:947
imt::base::hal::stm32f769::registers::DSIRegisters::LCOLCR
volatile DSI_LCOLCR LCOLCR
DSI Host LTDC Color Coding Register, Address offset: 0x10.
Definition DSIRegisters.h:945
imt::base::hal::stm32f769::registers::DSIRegisters::VVSACR
volatile DSI_VVSACR VVSACR
DSI Host Video VSA Configuration Register, Address offset: 0x54.
Definition DSIRegisters.h:959
imt::base::hal::stm32f769::registers::DSIRegisters::IER0
volatile DSI_IER0 IER0
DSI Host Interrupt Enable Register 0, Address offset: 0xC4.
Definition DSIRegisters.h:986
imt::base::hal::stm32f769::registers::DSIRegisters::reserved6
uint32_t volatile reserved6[7]
Reserved, 0x11C - 0x137.
Definition DSIRegisters.h:998
imt::base::hal::stm32f769::registers::DSIRegisters::PSR
volatile DSI_PSR PSR
DSI Host PHY Status Register, Address offset: 0xB0.
Definition DSIRegisters.h:982
imt::base::hal::stm32f769::registers::DSIRegisters::LPMCCR
volatile DSI_LPMCCR LPMCCR
DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118.
Definition DSIRegisters.h:997
imt::base::hal::stm32f769::registers::DSIRegisters::VLCR
volatile DSI_VLCR VLCR
DSI Host Video Line Configuration Register, Address offset: 0x50.
Definition DSIRegisters.h:958
imt::base::hal::stm32f769::registers::DSIRegisters::VLCCR
volatile DSI_VLCCR VLCCR
DSI Host Video Line Current Configuration Register, Address offset: 0x150.
Definition DSIRegisters.h:1005
imt::base::hal::stm32f769::registers::DSIRegisters::CCR
volatile DSI_CCR CCR
DSI HOST Clock Control Register, Address offset: 0x08.
Definition DSIRegisters.h:943
imt::base::hal::stm32f769::registers::DSIRegisters::reserved5
uint32_t volatile reserved5
Reserved, 0x114.
Definition DSIRegisters.h:996
imt::base::hal::stm32f769::registers::DSIRegisters::WIFCR
volatile DSI_WIFCR WIFCR
DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410.
Definition DSIRegisters.h:1017
imt::base::hal::stm32f769::registers::DSIRegisters::GVCIDR
volatile DSI_GVCIDR GVCIDR
DSI Host Generic VCID Register, Address offset: 0x30.
Definition DSIRegisters.h:950
imt::base::hal::stm32f769::registers::DSIRegisters::VNPCCR
volatile DSI_VNPCCR VNPCCR
DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144.
Definition DSIRegisters.h:1002
imt::base::hal::stm32f769::registers::DSIRegisters::ISR0
volatile DSI_ISR0 ISR0
DSI Host Interrupt & Status Register 0, Address offset: 0xBC.
Definition DSIRegisters.h:984
imt::base::hal::stm32f769::registers::DSIRegisters::LVCIDR
volatile DSI_LVCIDR LVCIDR
DSI Host LTDC VCID Register, Address offset: 0x0C.
Definition DSIRegisters.h:944
imt::base::hal::stm32f769::registers::DSIRegisters::DLTCR
volatile DSI_DLTCR DLTCR
DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C.
Definition DSIRegisters.h:977
imt::base::hal::stm32f769::registers::DSIRegisters::PCONFR
volatile DSI_PCONFR PCONFR
DSI Host PHY Configuration Register, Address offset: 0xA4.
Definition DSIRegisters.h:979
imt::base::hal::stm32f769::registers::DSIRegisters::VMCR
volatile DSI_VMCR VMCR
DSI Host Video Mode Configuration Register, Address offset: 0x38.
Definition DSIRegisters.h:952
imt::base::hal::stm32f769::registers::DSIRegisters::TDCR
volatile DSI_TDCR TDCR
DSI Host 3D Configuration Register, Address offset: 0x90.
Definition DSIRegisters.h:974
imt::base::hal::stm32f769::registers::DSIRegisters::VVACCR
volatile DSI_VVACCR VVACCR
DSI Host Video VA Current Configuration Register, Address offset: 0x160.
Definition DSIRegisters.h:1009
imt::base::hal::stm32f769::registers::DSIRegisters::WISR
volatile DSI_WISR WISR
DSI Wrapper Interrupt and Status Register, Address offset: 0x40C.
Definition DSIRegisters.h:1016
imt::base::hal::stm32f769::registers::DSIRegisters::LCCCR
volatile DSI_LCCCR LCCCR
DSI Host LTDC Current Color Coding Register, Address offset: 0x110.
Definition DSIRegisters.h:995
imt::base::hal::stm32f769::registers::DSIRegisters::reserved0
uint32_t volatile reserved0[4]
Reserved, 0x1C - 0x2B.
Definition DSIRegisters.h:948
imt::base::hal::stm32f769::registers::DSIRegisters::VHSACCR
volatile DSI_VHSACCR VHSACCR
DSI Host Video HSA Current Configuration Register, Address offset: 0x148.
Definition DSIRegisters.h:1003
imt::base::hal::stm32f769::registers::DSIRegisters::TDCCR
volatile DSI_TDCCR TDCCR
DSI Host 3D Current Configuration Register, Address offset: 0x190.
Definition DSIRegisters.h:1011
imt::base::hal::stm32f769::registers::DSIRegisters::reserved9
uint32_t volatile reserved9
Reserved, 0x414.
Definition DSIRegisters.h:1018
imt::base::hal::stm32f769::registers::DSIRegisters::GPDR
volatile DSI_GPDR GPDR
DSI Host Generic Payload Data Register, Address offset: 0x70.
Definition DSIRegisters.h:966
imt::base::hal::stm32f769::registers::DSIRegisters::CMCR
volatile DSI_CMCR CMCR
DSI Host Command Mode Configuration Register, Address offset: 0x68.
Definition DSIRegisters.h:964
imt::base::hal::stm32f769::registers::DSIRegisters::getInstance
static DSIRegisters & getInstance()
Gets the instance of the registers for the LTDC module.
Definition DSIRegisters.h:936
imt::base::hal::stm32f769::registers::DSIRegisters::TCCR4
volatile DSI_TCCR4 TCCR4
DSI Host Timeout Counter Configuration Register 4, Address offset: 0x88.
Definition DSIRegisters.h:972
imt::base::hal::stm32f769::registers::DSIRegisters::WRPCR
volatile DSI_WRPCR WRPCR
DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430.
Definition DSIRegisters.h:1025
imt::base::hal::stm32f769::registers::DSIRegisters::reserved3
uint32_t volatile reserved3[8]
Reserved, 0xE0 - 0xFF.
Definition DSIRegisters.h:991
imt::base::hal::stm32f769::registers::DSIRegisters::reserved1
uint32_t volatile reserved1[2]
Reserved, 0xB4 - 0xBB.
Definition DSIRegisters.h:983
imt::base::hal::stm32f769::registers::DSIRegisters::ISR1
volatile DSI_ISR1 ISR1
DSI Host Interrupt & Status Register 1, Address offset: 0xC0.
Definition DSIRegisters.h:985
imt::base::hal::stm32f769::registers::DSIRegisters::GPSR
volatile DSI_GPSR GPSR
DSI Host Generic Packet Status Register, Address offset: 0x74.
Definition DSIRegisters.h:967
imt::base::hal::stm32f769::registers::DSIRegisters::WIER
volatile DSI_WIER WIER
DSI Wrapper Interrupt Enable Register, Address offset: 0x408.
Definition DSIRegisters.h:1015
imt::base::hal::stm32f769::registers::DSIRegisters::WPCR3
volatile DSI_WPCR3 WPCR3
DSI Wrapper PHY Configuration Register 3, Address offset: 0x424.
Definition DSIRegisters.h:1022
imt::base::hal::stm32f769::registers::DSIRegisters::VCCR
volatile DSI_VCCR VCCR
DSI Host Video Chunks Configuration Register, Address offset: 0x40.
Definition DSIRegisters.h:954
imt::base::hal::stm32f769::registers::DSIRegisters::VPCCR
volatile DSI_VPCCR VPCCR
DSI Host Video Packet Current Configuration Register, Address offset: 0x13C.
Definition DSIRegisters.h:1000
imt::base::hal::stm32f769::registers::DSIRegisters::CLCR
volatile DSI_CLCR CLCR
DSI Host Clock Lane Configuration Register, Address offset: 0x94.
Definition DSIRegisters.h:975
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GHCR
DSI Host Generic Header Configuration Register (DSI_GHCR), chapter 20.15.24.
Definition DSIRegisters.h:250
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GHCR::reg
uint32_t volatile reg
Definition DSIRegisters.h:259
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GHCR::fields
Fields volatile fields
Definition DSIRegisters.h:258
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPDR
DSI Host Generic Payload Data Register (DSI_GPDR), chapter 20.15.25.
Definition DSIRegisters.h:265
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPDR::fields
Fields volatile fields
Definition DSIRegisters.h:272
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPDR::reg
uint32_t volatile reg
Definition DSIRegisters.h:273
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPSR
DSI Host Generic Packet Status Register (DSI_GPSR), chapter 20.15.26.
Definition DSIRegisters.h:279
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPSR::reg
uint32_t volatile reg
Definition DSIRegisters.h:291
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_GPSR::fields
Fields volatile fields
Definition DSIRegisters.h:290
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0
DSI Host Interrupt Enable Register 0 (DSI_IER0), chapter 20.15.43.
Definition DSIRegisters.h:510
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::fields
Fields volatile fields
Definition DSIRegisters.h:541
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::reg
uint32_t volatile reg
Definition DSIRegisters.h:542
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER0::bits
Bits volatile bits
Definition DSIRegisters.h:540
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1
DSI Host Interrupt Enable Register 1 (DSI_IER1), chapter 20.15.44.
Definition DSIRegisters.h:548
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::fields
Fields volatile fields
Definition DSIRegisters.h:565
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_IER1::reg
uint32_t volatile reg
Definition DSIRegisters.h:566
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0
DSI Host Interrupt & Status Register 0 (DSI_ISR0), chapter 20.15.41.
Definition DSIRegisters.h:448
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::bits
Bits volatile bits
Definition DSIRegisters.h:478
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::reg
uint32_t volatile reg
Definition DSIRegisters.h:480
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR0::fields
Fields volatile fields
Definition DSIRegisters.h:479
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1
DSI Host Interrupt & Status Register 1 (DSI_ISR1), chapter 20.15.42.
Definition DSIRegisters.h:486
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::reg
uint32_t volatile reg
Definition DSIRegisters.h:504
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_ISR1::bits
Bits volatile bits
Definition DSIRegisters.h:503
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCR
DSI Host Protocol Configuration Register (DSI_PCR), chapter 20.15.8.
Definition DSIRegisters.h:84
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCR::bits
Bits volatile bits
Definition DSIRegisters.h:93
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PCR::reg
uint32_t volatile reg
Definition DSIRegisters.h:94
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PUCR
DSI Host PHY ULPS Control Register (DSI_PUCR), chapter 20.15.38.
Definition DSIRegisters.h:409
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PUCR::reg
uint32_t volatile reg
Definition DSIRegisters.h:418
imt::base::hal::stm32f769::registers::DSIRegisters::DSI_PUCR::bits
Bits volatile bits
Definition DSIRegisters.h:417