DSI Wrapper PHY Configuration Register 1 (DSI_WPCR1), chapter 20.16.7. More...

#include <Imt.Base.HAL.STM32F769/Registers/DSIRegisters.h>

Public Attributes
uint32_t volatile	HSTXDCL: 2
	High-Speed Transmission Delay on Clock Lane.

uint32_t volatile	HSTXDDL: 2
	High-Speed Transmission Delay on Data Lanes.

uint32_t	volatile: 2

uint32_t volatile	LPSRCCL: 2
	Low-Power transmission Slew Rate Compensation on Clock Lane.

uint32_t volatile	LPSRCDL: 2
	Low-Power transmission Slew Rate Compensation on Data Lanes.

uint32_t volatile	SDDC: 1
	SDD Control.

uint32_t volatile	LPRXVCDL: 2
	Low-Power Reception V-IL Compensation on Data Lanes: information from QubeMx Example HAL.

uint32_t volatile	HSTXSRCCL: 2
	High-Speed Transmission slew-rate control on Clock Lane.

uint32_t volatile	HSTXSRCDL: 2
	High-Speed Transmission slew-rate control on Data Lanes.

uint32_t volatile	FLPRXLPM: 1
	Forces LP Receiver in Low-Power Mode.

uint32_t volatile	LPRXFT: 2
	Low-Power RX low-pass Filtering Tuning.

Detailed Description

DSI Wrapper PHY Configuration Register 1 (DSI_WPCR1), chapter 20.16.7.

Definition at line 870 of file DSIRegisters.h.

Member Data Documentation

◆ FLPRXLPM

uint32_t volatile imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::FLPRXLPM

Forces LP Receiver in Low-Power Mode.

Definition at line 883 of file DSIRegisters.h.

◆ HSTXDCL

uint32_t volatile imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::HSTXDCL

High-Speed Transmission Delay on Clock Lane.

Definition at line 871 of file DSIRegisters.h.

◆ HSTXDDL

uint32_t volatile imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::HSTXDDL

High-Speed Transmission Delay on Data Lanes.

Definition at line 872 of file DSIRegisters.h.

◆ HSTXSRCCL

uint32_t volatile imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::HSTXSRCCL

High-Speed Transmission slew-rate control on Clock Lane.

Definition at line 880 of file DSIRegisters.h.

◆ HSTXSRCDL

uint32_t volatile imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::HSTXSRCDL

High-Speed Transmission slew-rate control on Data Lanes.

Definition at line 881 of file DSIRegisters.h.

◆ LPRXFT

uint32_t volatile imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::LPRXFT

Low-Power RX low-pass Filtering Tuning.

Definition at line 885 of file DSIRegisters.h.

◆ LPRXVCDL

uint32_t volatile imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::LPRXVCDL

Low-Power Reception V-IL Compensation on Data Lanes: information from QubeMx Example HAL.

Definition at line 879 of file DSIRegisters.h.

◆ LPSRCCL

uint32_t volatile imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::LPSRCCL

Low-Power transmission Slew Rate Compensation on Clock Lane.

Definition at line 874 of file DSIRegisters.h.

◆ LPSRCDL

uint32_t volatile imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::LPSRCDL

Low-Power transmission Slew Rate Compensation on Data Lanes.

Definition at line 875 of file DSIRegisters.h.

◆ SDDC

uint32_t volatile imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::SDDC

SDD Control.

Definition at line 877 of file DSIRegisters.h.

◆ volatile

uint32_t imt::base::hal::stm32f769::registers::DSIRegisters::DSI_WPCR1::volatile

reserved

Definition at line 873 of file DSIRegisters.h.

The documentation for this struct was generated from the following file:

C:/src/imt/Imt.Base-cpp/Imt.Base/Imt.Base.HAL.STM32F769/Registers/DSIRegisters.h

Public Attributes