OSPIRegisters.h

Go to the documentation of this file.

// (c) IMT - Information Management Technology AG, CH-9470 Buchs, www.imt.ch.
 
#ifndef STM32H730_OSPIREGISTERS_H
#define STM32H730_OSPIREGISTERS_H
 
#include <Imt.Base.Core.Platform/Platform.h>
#include <Imt.Base.HAL.STM32H730/SystemMemoryMap.h>
 
namespace imt {
namespace base {
namespace hal {
namespace stm32h730 {
namespace registers {
 
struct OSPIRegisters {
    struct OCTOSPI_CR {
        uint32_t volatile EN     : 1; 
        uint32_t volatile ABORT  : 1; 
        uint32_t volatile DMAEN  : 1; 
        uint32_t volatile TCEN   : 1; 
        uint32_t volatile        : 2; 
        uint32_t volatile DQM    : 1; 
        uint32_t volatile FSEL   : 1; 
        uint32_t volatile FTHRES : 5; 
        uint32_t volatile        : 3; 
        uint32_t volatile TEIE   : 1; 
        uint32_t volatile TCIE   : 1; 
        uint32_t volatile FTIE   : 1; 
        uint32_t volatile SMIE   : 1; 
        uint32_t volatile TOIE   : 1; 
        uint32_t volatile        : 1; 
        uint32_t volatile APMS   : 1; 
        uint32_t volatile PMM    : 1; 
        uint32_t volatile        : 4; 
        uint32_t volatile FMODE  : 2; 
        uint32_t volatile        : 2; 
    };
 
    struct OCTOSPI_DCR1 {
        uint32_t volatile CKMODE  : 1; 
        uint32_t volatile FRCK    : 1; 
        uint32_t volatile         : 1; 
        uint32_t volatile DLYBYP  : 1; 
        uint32_t volatile         : 4; 
        uint32_t volatile CSHT    : 6; 
        uint32_t volatile         : 2; 
        uint32_t volatile DEVSIZE : 5; 
        uint32_t volatile         : 3; 
        uint32_t volatile MTYP    : 3; 
        uint32_t volatile         : 5; 
    };
 
    struct OCTOSPI_DCR2 {
        uint32_t volatile PRESCALER : 8;  
        uint32_t volatile           : 8;  
        uint32_t volatile WRAPSIZE  : 3;  
        uint32_t volatile           : 13; 
    };
 
    struct OCTOSPI_DCR3 {
        uint32_t volatile MAXTRAN : 8;  
        uint32_t volatile         : 8;  
        uint32_t volatile CSBOUND : 5;  
        uint32_t volatile         : 11; 
    };
 
    struct OCTOSPI_DCR4 {
        uint32_t volatile REFRESH : 32; 
    };
 
    struct OCTOSPI_SR {
        uint32_t volatile TEF    : 1;  
        uint32_t volatile TCF    : 1;  
        uint32_t volatile FTF    : 1;  
        uint32_t volatile SMF    : 1;  
        uint32_t volatile TOF    : 1;  
        uint32_t volatile BUSY   : 1;  
        uint32_t volatile        : 2;  
        uint32_t volatile FLEVEL : 6;  
        uint32_t volatile        : 18; 
    };
 
    struct OCTOSPI_FCR {
        uint32_t volatile CTEF : 1;  
        uint32_t volatile CTCF : 1;  
        uint32_t volatile      : 1;  
        uint32_t volatile CSMF : 1;  
        uint32_t volatile CTOF : 1;  
        uint32_t volatile      : 27; 
    };
 
    struct OCTOSPI_DLR {
        uint32_t volatile DL : 32; 
    };
 
    struct OCTOSPI_AR {
        uint32_t volatile ADDRESS : 32; 
    };
 
    struct OCTOSPI_DR {
        uint32_t volatile DATA : 32; 
    };
 
    struct OCTOSPI_PSMKR {
        uint32_t volatile MASK : 32; 
    };
 
    struct OCTOSPI_PSMAR {
        uint32_t volatile MATCH : 32; 
    };
 
    struct OCTOSPI_PIR {
        uint32_t volatile INTERVAL : 16; 
        uint32_t volatile          : 16; 
    };
 
    union OCTOSPI_CCR {
        struct Fields {
            uint32_t volatile IMODE  : 3; 
            uint32_t volatile IDTR   : 1; 
            uint32_t volatile ISIZE  : 2; 
            uint32_t volatile        : 2; 
            uint32_t volatile ADMODE : 3; 
            uint32_t volatile ADDTR  : 1; 
            uint32_t volatile ADSIZE : 2; 
            uint32_t volatile        : 2; 
            uint32_t volatile ABMODE : 3; 
            uint32_t volatile ABDTR  : 1; 
            uint32_t volatile ABSIZE : 2; 
            uint32_t volatile        : 2; 
            uint32_t volatile DMODE  : 3; 
            uint32_t volatile DDTR   : 1; 
            uint32_t volatile        : 1; 
            uint32_t volatile DQSE   : 1; 
            uint32_t volatile        : 1; 
            uint32_t volatile SIOO   : 1; 
        };
        Fields volatile field;
        uint32_t volatile reg;
    };
 
    struct OCTOSPI_TCR {
        uint32_t volatile DCYC   : 5;  
        uint32_t volatile        : 23; 
        uint32_t volatile DHQC   : 1;  
        uint32_t volatile        : 1;  
        uint32_t volatile SSHIFT : 1;  
        uint32_t volatile        : 1;  
    };
 
    struct OCTOSPI_IR {
        uint32_t volatile INSTRUCTION : 32; 
    };
 
    struct OCTOSPI_ABR {
        uint32_t volatile ALTERNATE : 32; 
    };
 
    struct OCTOSPI_LPTR {
        uint32_t volatile TIMEOUT : 16; 
        uint32_t volatile         : 16; 
    };
 
    struct OCTOSPI_WPCCR {
        uint32_t volatile IMODE  : 3; 
        uint32_t volatile IDTR   : 1; 
        uint32_t volatile ISIZE  : 2; 
        uint32_t volatile        : 2; 
        uint32_t volatile ADMODE : 3; 
        uint32_t volatile ADDTR  : 1; 
        uint32_t volatile ADSIZE : 2; 
        uint32_t volatile        : 2; 
        uint32_t volatile ABMODE : 3; 
        uint32_t volatile ABDTR  : 1; 
        uint32_t volatile ABSIZE : 2; 
        uint32_t volatile        : 2; 
        uint32_t volatile DMODE  : 3; 
        uint32_t volatile DDTR   : 1; 
        uint32_t volatile        : 1; 
        uint32_t volatile DQSE   : 1; 
        uint32_t volatile        : 2; 
    };
 
    struct OCTOSPI_WPTCR {
        uint32_t volatile DCYC   : 5;  
        uint32_t volatile        : 23; 
        uint32_t volatile DHQC   : 1;  
        uint32_t volatile        : 1;  
        uint32_t volatile SSHIFT : 1;  
        uint32_t volatile        : 1;  
    };
 
    struct OCTOSPI_WPIR {
        uint32_t volatile INSTRUCTION : 32; 
    };
 
    struct OCTOSPI_WPABR {
        uint32_t volatile ALTERNATE : 32; 
    };
 
    struct OCTOSPI_WCCR {
        uint32_t volatile IMODE  : 3; 
        uint32_t volatile IDTR   : 1; 
        uint32_t volatile ISIZE  : 2; 
        uint32_t volatile        : 2; 
        uint32_t volatile ADMODE : 3; 
        uint32_t volatile ADDTR  : 1; 
        uint32_t volatile ADSIZE : 2; 
        uint32_t volatile        : 2; 
        uint32_t volatile ABMODE : 3; 
        uint32_t volatile ABDTR  : 1; 
        uint32_t volatile ABSIZE : 2; 
        uint32_t volatile        : 2; 
        uint32_t volatile DMODE  : 3; 
        uint32_t volatile DDTR   : 1; 
        uint32_t volatile        : 1; 
        uint32_t volatile DQSE   : 1; 
        uint32_t volatile        : 2; 
    };
 
    struct OCTOSPI_WTCR {
        uint32_t volatile DCYC : 5;  
        uint32_t volatile      : 27; 
    };
 
    struct OCTOSPI_WIR {
        uint32_t volatile INSTRUCTION : 32; 
    };
 
    struct OCTOSPI_WABR {
        uint32_t volatile ALTERNATE : 32; 
    };
 
    struct OCTOSPI_HLCR {
        uint32_t volatile LM   : 1; 
        uint32_t volatile WZL  : 1; 
        uint32_t volatile      : 6; 
        uint32_t volatile TACC : 8; 
        uint32_t volatile TRWR : 8; 
        uint32_t volatile      : 8; 
    };
 
    static OSPIRegisters& getInstance(OCTOSPIModuleAddress const module) {
        return *reinterpret_cast<OSPIRegisters*>(module);
    }
 
    // Registers
    volatile OCTOSPI_CR CR;            // Offset 0x00
    uint32_t volatile _reserved0;      // Offset 0x04
    volatile OCTOSPI_DCR1 DCR1;        // Offset 0x08
    volatile OCTOSPI_DCR2 DCR2;        // Offset 0x0C
    volatile OCTOSPI_DCR3 DCR3;        // Offset 0x10
    volatile OCTOSPI_DCR4 DCR4;        // Offset 0x14
    uint32_t volatile _reserved1[2];   // Offset 0x18
    volatile OCTOSPI_SR SR;            // Offset 0x20
    volatile OCTOSPI_FCR FCR;          // Offset 0x24
    uint32_t volatile _reserved2[6];   // Offset 0x28
    volatile OCTOSPI_DLR DLR;          // Offset 0x40
    uint32_t volatile _reserved3;      // Offset 0x44
    volatile OCTOSPI_AR AR;            // Offset 0x48
    uint32_t volatile _reserved4;      // Offset 0x4C
    volatile OCTOSPI_DR DR;            // Offset 0x50
    uint32_t volatile _reserved5[11];  // Offset 0x54
    volatile OCTOSPI_PSMKR PSMKR;      // Offset 0x80
    uint32_t volatile _reserved6;      // Offset 0x84
    volatile OCTOSPI_PSMAR PSMAR;      // Offset 0x88
    uint32_t volatile _reserved7;      // Offset 0x8C
    volatile OCTOSPI_PIR PIR;          // Offset 0x90
    uint32_t volatile _reserved8[27];  // Offset 0x94
    volatile OCTOSPI_CCR CCR;          // Offset 0x100
    uint32_t volatile _reserved9;      // Offset 0x104
    volatile OCTOSPI_TCR TCR;          // Offset 0x108
    uint32_t volatile _reserved10;     // Offset 0x10C
    volatile OCTOSPI_IR IR;            // Offset 0x110
    uint32_t volatile _reserved11[3];  // Offset 0x114
    volatile OCTOSPI_ABR ABR;          // Offset 0x120
    uint32_t volatile _reserved12[3];  // Offset 0x124
    volatile OCTOSPI_LPTR LPTR;        // Offset 0x130
    uint32_t volatile _reserved13[3];  // Offset 0x134
    volatile OCTOSPI_WPCCR WPCCR;      // Offset 0x140
    uint32_t volatile _reserved14;     // Offset 0x144
    volatile OCTOSPI_WPTCR WPTCR;      // Offset 0x148
    uint32_t volatile _reserved15;     // Offset 0x14C
    volatile OCTOSPI_WPIR WPIR;        // Offset 0x150
    uint32_t volatile _reserved16[3];  // Offset 0x154
    volatile OCTOSPI_WPABR WPABR;      // Offset 0x160
    uint32_t volatile _reserved17[7];  // Offset 0x164
    volatile OCTOSPI_WCCR WCCR;        // Offset 0x180
    uint32_t volatile _reserved18;     // Offset 0x184
    volatile OCTOSPI_WTCR WTCR;        // Offset 0x188
    uint32_t volatile _reserved19;     // Offset 0x18C
    volatile OCTOSPI_WIR WIR;          // Offset 0x190
    uint32_t volatile _reserved20[3];  // Offset 0x194
    volatile OCTOSPI_WABR WABR;        // Offset 0x1A0
    uint32_t volatile _reserved21[23]; // Offset 0x1A4
    volatile OCTOSPI_HLCR HLCR;        // Offset 0x200
 
private:
 
    OSPIRegisters();
 
    OSPIRegisters(OSPIRegisters const& other);
 
    OSPIRegisters& operator=(OSPIRegisters const& other);
};
 
} // namespace registers
} // namespace stm32h730
} // namespace hal
} // namespace base
} // namespace imt
 
#endif // STM32H730_OSPIREGISTERS_H