Class List

Here are the classes, structs, unions and interfaces with brief descriptions:

[detail level 123456789]

▼Nimt	This is a application specific file which is used to configure Imt.Base.Core.Math
▼Nbase
▼Ncore
►Ndiagnostics
►Ntest
CMemoryLeakDetector	Provides a class that can be used to easily detect memory leaks
►CAssertActionManager	The AssertActionManager defines some events called AssertActionEvents for which functions can be registered
CAssertEventLimits	Limits for AssertEvent enum
►Nmath
CMaths	Mathematical utility functions
CMathUtils	Mathematical utility functions
►Nplatform
CCppVersion	Provides check for the C++ version suppoprted by the compiler according to cpp reference
CNoncopyable	Base class for a non copyable class that disables copy and assignment of instances
CNonmovable	Base class for a not movable class that disables copy, assignment and move of instances
CStaticClass	Base class for a static class that disables construction, copy, assignment and move of instances
CVersion	Static class with version informations on the Imt.Base libraries
►Nserialization
CDeserializer	Deserializes various data types from the given byte buffer
CSerializableIfc	Serialization is the process of translating data structures into a binary representation
CSerializableSenderIfc	Interface to write a serializable object to another object
CSerializer	Serializes various data types into the given byte buffer
►Nutil
CBitUtil	Bit Utility class pure static class
CByteWordUtil	Contains some helpful converting tools
CCharUtil	String Utility class pure static class
CCrc	Cyclic redundancy check (CRC) See (german): http://de.wikipedia.org/wiki/Zyklische_Redundanzpr%C3%BCfung
CDateTimeStamp	Class to access date and time information
CDequeue	Dequeue, Queue able to pop/push elements either from front or back
CFlags	A template to create a type safe flags type from an enum
CGenerateBitMask	Generates a bit mask of the given width left shifted offset bits from the least significant bit position of the word
CGenerateUnshiftedBitMask	Generates a bit mask of the given width whose least significant bit is at the same bit position as the least significant bit of the word
CGenerateUnshiftedBitMask< 0 >
CKeyWriteOnlyPolicy	A write-only mutability policy to enable writing registers like new reset register
CListNode	Node used for LinkedList class
CListNode< T, LinkedListType::SINGLE >	Node used for LinkedList class
CListNode< T, LinkedListType::DOUBLE >	Node used for LinkedList class
►CLinkedList	Linked list
CIterator	LinkedList class iterator
CMD5	This class provides the MD5 checksum calculation routines
CMinMax	Min/Max utility class
CPoolAllocator	Fixed size pool allocator
CRange	A range of values limited by an lower and upper value that is included in the range
CReadOnlyPolicy	A read-only mutability policy for use with Register template
CReadWritePolicy	A read-write mutability policy for use with Register template
CRegister	Template to define register at runtime, by providing the mutability policy, like Read Only/Write Only/Read Write etc, address, offset and width
CRingBuffer	This template class implements a FIFO ringbuffer
CSpan	This template class provides a small wrapper around a data buffer
CCrtpHelper	Requires == from the underlying type and provides == and !=
CIgnore1
CIgnore2
CIgnore3
CIgnore4
CIgnore5
CIgnore6
CIgnore7
CIgnore8
CIgnore9
CIgnore10
CEqualityComparable	Requires == from the underlying type and provides == and !=
CLessThanComparable	Requires < from the underlying type and provides <, >, <=, >=
CTotallyOrdered	Provides ==, !=, <, >, <=, >=
CAddable	Requires +, += from the underlying type and provides +, +=
CSubtractable	Requires -, -= from the underlying type and provides -, -=
CAdditive	Groups Addable and Subtractable to one skill
CMultipliable	Requires * from the underlying type and provides *
CDividable	Requires / from the underlying type and provides /
CMultiplicative	Groups Multipliable and Dividable to one skill
CArithmetic	Additive and Multiplicative to one skill
CIncrementable	Requires ++i from the underlying type and provides ++i, i++
CDecrementable	Requires –i from the underlying type and provides –i, i–
CUnitStepable	Groups imt::base::core::util::Incrementable and imt::base::core::util::Decrementable to one skill
CStrongTypedef	Prevent bugs at compile time by providing strongly-typed and expressive interfaces with zero overhead
CVersionInfo	Provides version information in simple class
CWriteOnlyPolicy	A write-only mutability policy for use with Register template
▼Ndff
►Nactiveparts
►Ntest
CChannelConnectionVerifier	Helper class to verify that the ports are properly connected with channels
CChannelMockIn	Mocking input channel for unit test which allows to pass data to the input port
►CChannelMockOut	Mocking output channel for unit test which stores the received data
CDataContainer	Structure which stores the received data received on the channel
CEventArgsSerializer	Helper class for passing serializable data and getting a deserializer
►CTestLoggerAP	Test logger for unit test which registers itself as Logger in Runtime and stores the received log entries
CLogEntryContainer	Container which stores the received data
CActivePartAbs	Abstract base class for an ActivePart
CActivePartContainerAbs	A container groups several elements together (usually ActiveParts)
CChannelIfc	Interface of a channel to transmit data to a receiver
CChannelInternalForwarder	ChannelInternalForwarder handles the following situations
CChannelOneToAny	Send the message on a One-to-Any channel (multiple receivers)
CChannelOneToNull	Used to connect an output port that is not used to a sink
CChannelOneToOne	Send the message on a One-to-One channel
COneShotTimer	A one shot timer to be used in an active part
CPeriodicTimer	A periodic timer to be used in an active part
CPortInput	Messages can be received on the input port
CPortInputSplit	Splits a message to multiple input ports
CPortOutput	Messages can be sent on the output port
CPortOutputJoin	Joins multiple PortOutputs to a single
CReceiverIfc	Interface for any receiver
CVariableOneShotTimer	A one shot timer to be used in an active part
►Nruntime
►Narm
►Ncortexm
CGenericPowerSaveIdleCallback	Generic power save callback implementation for ARM Cortex-M runtime
►Nmock
►CRuntimeMock	Mocking object which stores all relevant information for runtime
CEventData	Container which stores the received data
CTimerServiceIfc	Interface to start timer
CEventData	Event data structure base
CEventDataNormal	Event data structure for normal sized buffer
CEventIfc	Interface for any event data
CEventPoolCapacityCallbackIfc	Interface for callback about the event pool capacity
►CEventReadyList	Class to store EventData-pointers according to their priority
CNode	Internal structure to store event pointers as list, public only because of the pool initialization in the constructor
►CExecutableConfiguration	Optional parameters that can be passed from the active part to the runtime to be considered when creating the executable (task, thread, ect.) for the specific runtime
CCoreAffinity	Data type to pass the core affinity
CStackSize	Size type to pass the stack size
CTimeSlice	Size type to pass the time slice
CExecutableIfc	Interface of an executable which is called by the runtime once an event has to be processed
CFreeRunningTimer	Representation of a free running timer module in ticks, which keeps repeatedly running
CIdleCallbackIfc	Interface for idle processing
CRuntimeCore	RuntimeCore defines the basic Application Interface (API) to the core part of the event-based run to completion (RTC) kernel
CRuntimeCriticalSection	Class for handling critical sections
CRuntimeEventPools	Holds the internal global event pools for the runtime
CRuntimeIdGenerator	RuntimeIdGenerator defines the basic Application Interface (API) to the id generation part of the run to completion (RTC) kernel
CRuntimeInterrupts	RuntimeInterrupts defines the basic Application Interface (API) to the interrupt part of the run to completion (RTC) kernel
CRuntimeLog	Implementation of a simple centralized logging mechanism
CRuntimePools	Runtime executable for binary user specific allocation
CRuntimePriorityLimits	Limits for RuntimePriority
CRuntimeProtocolIdentifiers	Identifiers of protocols used in run to completion (RTC) kernel
CRuntimeStatistics	Holds the data for the runtime statistics
CRuntimeStatisticsCpu	Holds the data for the cpu usage statistics
CRuntimeStatisticsEvents	Holds the data for the event usage statistics
CRuntimeStatisticsExecutables	Holds the data for the executable execution statistics
CRuntimeStatisticsTimers	Holds the data for the timer usage statistics
►CRuntimeTimer	RuntimeTimer defines the basic Application Interface (API) to the timer part of the run to completion (RTC) kernel
CTimeItem	TimeItem Object Structure
CRuntimeTimerEvent	Event arguments which are passed when a timer is fired
▼Nhal
►Nstm32f030
►Nmock
CSTM32F030Mock	Mocking object which stores all relevant information for STM32F030 HAL
►Nstm32f103
►Nmock
CSTM32F103Mock	Mocking object which stores all relevant information for STM32F103 HAL
►Nstm32f767
►Nmock
CMockADC	Mock implementation for the ADC module
►CMockCAN	USART mock implementation
CCanModule	Enumeration of the available USART/UART modules on STM32F767
CFilterSettings
CMockDAC	Mock implementation for the DAC module
CMockDMA	DMA mock implementation
CMockEXTI	Mock implementation for the EXTI module
►CMockFLASH	Mock implementation for the FLASH module
CFlashSectorAddress
CMockGPIO	Mock implementation for a GPIO module
CMockI2C	I2C mock implementation
CMockI2S	I2S mock implementation
CMockNVIC	Mock implementation for the NVIC module
CMockPWR	Mock implementation for PWR
CMockRCC	Mock implementation for the RCC module
CMockRTC	Mock implementation for the RTC module
CMockSPI	Mock implementation for the SPI module
CMockSYSCFG	Mock implementation for SYSCFG controller
CMockSYSTICK	Mock implementation for SYSTICK module
CMockTIM	Mock implementation for the TIM module
CMockUSART	USART mock implementation
CMockUSB	USB mock implementation
CSTM32F767Mock	Mocking object which stores all relevant information for STM32F767 HAL
►Nstm32f769
►Nmock
CMockADC	Mock implementation for the ADC module
CMockDMA	DMA mock implementation
CMockEXTI	Mock implementation for the EXTI module
►CMockFLASH	Mock implementation for the FLASH module
CFlashSectorAddress
CMockGPIO	Mock implementation for a GPIO module
CMockNVIC	Mock implementation for the NVIC module
CMockPWR	Mock implementation for PWR
CMockRCC	Mock implementation for the RCC module
CMockSDMMC	Mock implementation for the SDMMC module
CMockSPI	Mock implementation for the SPI module
CMockSYSCFG	Mock implementation for SYSCFG controller
CMockSYSTICK	Mock implementation for SYSTICK module
CMockTIM	Mock implementation for the ADC module
►CMockUSART	USART mock implementation
CUsartModule	Enumeration of the available USART/UART modules on STM32F769
CSTM32F769Mock	Mocking object which stores all relevant information for STM32F769 HAL
►Nperipherals
►CADC	Analog Digital Converter (ADC) module
CChannel	Enumeration for ADC External Trigger Edge
CClockPrescaler	Enumeration for ADC Clock Prescaler
CDataAlign	Enumeration for ADC Data Alignment
CDMAAccessMode	Enumeration for ADC DMA access mode
CEndOfConversion	Enumeration for ADC End of Conversion flags
CFlagBit	ADC status register flags
CInitCommonStruct	ADC init common structure definition
CInitInjectedChannelStruct	ADC init injected channel structure definition
CInitInjectedStruct	ADC init injected structure definition
CInitRegularChannelStruct	ADC init regular channel structure definition
CInitRegularStruct	ADC init regular structure definition
CInitStruct	ADC init structure definition
CInjectedRank	Enumeration for ADC injected rank
CInjectedTriggerSource	Enumeration for ADC external injected trigger source
CInterruptBit	Enumeration for ADC interrupt
CMultiMode	Enumeration for ADC multi mode All other combinations are reserved and must not be programmed
CRegularRank	Enumeration for ADC regular rank
CRegularTriggerSource	Enumeration for ADC External Trigger Source
CResolution	Enumeration for ADC Resolutions
CSamplingDelay	Enumeration for ADC sampling delay
CSamplingTime	Enumeration for ADC sampling times
CTriggerEdge	Enumeration for ADC External Trigger Edge Injected & Regular
CBKPSRAM	Backup SRAM module
►CCAN	Controller area network(CAN) module register structure
CAutomaticBusOffManagement	Automatic bus-off management
CAutomaticWakeUpMode	Automatic wakeup mode
CBaudratePrescaler	The baud rate prescaler defines the length of a time quanta t_q = (BRP + 1) x t_PCLK
CCanRxMsg	CAN Rx message structure definition
CCanTxMsg	CAN Tx message structure definition
CErrorFlags	Enumeration for CAN error flags
CFifoAssignement	Filter FIFO assignement
CFilterActivation	Filter activation
CFilterBankRegister	Filter Bank Configuration
CFilterInitStruct	CAN filter init structure definition
CFilterMode	Filter Mode
CFilterNumber	CAN Filter number
CFilterScale	Filter Scale
CFrameLength	CAN frame length
CIdentifierType	CAN identifier type
CInitStruct	CAN Init structure definition
CInterruptConfig	Enumeration for CAN interrupt config identifiers
CLoopBackMode	Loop back mode (debug)
CNoAutomaticRetransmission	No automatic retransmission
CRemoteTransmission	CAN remote transmission
CRxFifo	CAN used rx FIFO for receiving
CRxFifoLockedMode	Received FIFO locked mode
CSilentMode	Silent mode (debug)
CTimeQuanta	Time Quanta
CTimeTriggeredCommunicationMode	Time triggered communication mode
CTransmitFlags	Enumeration for CAN transmission flags
CTxFifoPriority	Transmit FIFO priority
CTxMailbox	CAN used mailbox for transmission
►CCRC	Cyclic redundancy check calculation (CRC)module
CInitStruct	CRC Init structure definition
CPolynomialSize	Enumeration for Polynomial Size
CReverseInputData	Enumeration for Reverse input data
CReverseOutputData	Enumeration for Reverse output data
►CDAC	Digital Analog Converter (DAC) module
CAlignment	Enumeration for DAC data alignment
CChannel	Enumeration for DAC Channels
CChannelConfigStruct	DAC config channel structure definition
CTrigger	Enumeration for DAC trigger
CDBG	Debug Hardware abstaction layer Reference: ST_CortexM7_STM32F769_TRM_Rev2.pdf Chapter 44
►CDMA	Direct memory access controller DMA Reference: ST_CortexM7_STM32F769_TRM_Rev4.pdf Chapter 8
CBurst	Enumeration for DMA Burst Selection
CChannel	Enumeration for DMA Channel
CConfigStruct	DMA Config structure definition
CDataSize	Enumeration for DMA Peripheral Data Size Selection
CDirection	Enumeration for DMA Direction Selection
CFIFOMode	Enumeration for DMA FIFO Mode Selection
CFIFOThreshold	Enumeration for DMA FIFO Threshold Selection
CInitStruct	DMA Init structure definition
CIRQ	Enumeration of available IRQ for DMA
CMemoryIncrementedMode	Enumeration for Memory Incremented Mode Enable
CMode	Enumeration for DMA Mode Selection
CPeripheralIncrementedMode	Enumeration for Peripheral Incremented Mode Enable
CPriority	Enumeration for DMA Priority Selection
►CDMA2D	Chrom-art Accelerator (DMA2D) module register structure The naming of the fields is according to documentation and does not adhere to the coding style to allow using CTRL+F to find the name in the PDF
CAlphaInverted	Enumeration for DMA2D Alpha Inverted
CAlphaMode	Enumeration for DMA2D Alpha Mode
CClutColorMode	Enumeration for CLUT Color Mode
CColorMode	Enumeration for DMA2D Color Mode
CDma2DState	Enumeration for DMA2D State
CInitStruct	DMA2D Init structure definition
CLayer	Enumeration for DMA2D Layer
CLayerColorMode	Enumeration for DMA2D Foreground color format
CLayerConfigStruct	DMA2D Layer configuration structure definition
CLUTConfigStruct	DMA2D LUT configuration structure definition
CMode	Enumeration for DMA2D Mode
CRedBlueSwap	Enumeration for DMA2D Red Blue Swap
►CDSI	Display Serial Interface (DSI) module
►CError	DSI Error Data Type
CBit
CState	DSI States Structure definition
CDSIIrqIfc
►CDSITypes	Types for Display Serial Interface (DSI) module
CClockLaneCtrl	DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
CCmdCfgTypeDef
CDsiLongPktWrite	DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
CDsiPllInputClockDivider	Enumeration for DSI PLL Input Clock Divider Configuration
CDsiPllOutputClockDivider	Enumeration for DSI PLL Output Clock Divider Configuration
CDsiShortPktWrite	DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
CHOST_TimeoutTypeDef	DSI HOST Timeouts definition
CInitTypeDef	DSI Init Structure definition
CLPCmdTypeDef	DSI command transmission mode configuration
CNumberOfLanes	Enumeration for DSI number of Lanes
CPHY_TimerTypeDef	DSI PHY Timings definition
CPLLConfigStruct	DSI PLL Clock structure definition
CPolarity	Enumeration for Pin Polarity
CRgbColorCoding	Enumeration for DSI Color Coding
CTearingEffectSource
CVidCfgTypeDef	DSI Video mode configuration
CVideoModeType	Enumeration for DSI Video Mode Type
►CEXTI	External interrupt/event controller (EXTI) The external interrupt/event controller consists of up to 25 edge detectors for generating event / interrupt requests.Each input line can be independently configured to select the type (interrupt or event) and the corresponding trigger event(rising or falling or both).Each line can also masked independently
CInitStruct	EXTI initialization structure definition
CLineSelection	Enumeration availabe EXTI lines on the EXTI module
CMode	Enumeration of the available EXTI modes
CTrigger	Enumeration available interrupt trigger selection
►CFLASH	Embedded FLASH memory (FLASH)
CARTEnable	Enumeration for Enable
CFlashKey	Flash unlock keys
CFlashSectorAddress	Flash sector addresses
CInterrupt	Avaiable interrupts on the flash module
CLatency	Enumeration for FLASH Latency
COperation	Available operations
CStatusFlag	Avaiable status flags on the flash module
►CFMC	(FMC) module register structure
CSDRAM_Bank	Enumeration for FMC SDRAM Banks
CSDRAM_BurstRead	Enumeration for FMC SDRAM Burst read This bit enables burst read mode.The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO
CSDRAM_CASLatency	Enumeration for FMC SDRAM CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles
CSDRAM_ClockConfiguration	Enumeration for FMC SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling before changing the frequency.In this case the SDRAM must be re - initialized
CSDRAM_ColumnAddressBits	Enumeration for FMC SDRAM Colum Address Bits These bits define the number of bits of a column address
CSDRAM_CommandMode	Enumeration for FMC SDRAM Command mode These bits define the command issued to the SDRAM device
CSDRAM_CommandStruct	FMC SDRAM Command structure definition
CSDRAM_CommandTarget	Enumeration for FMC SDRAM Command Target These bits define the command issued to the SDRAM device
CSDRAM_DelayCycles	Enumeration for FMC SDRAM Delay Cycles
CSDRAM_InitStruct	FMC SDRAM Init structure definition
CSDRAM_MemoryDataBusWidth	Enumeration for FMC SDRAM Memory data bus width These bits define the memory device width
CSDRAM_NumberInternalBanks	Enumeration for FMC SDRAM Number of internal banks This bit sets the number of internal banks
CSDRAM_ReadPipeDelay	Enumeration for FMC SDRAM Read pipe These bits define the delay, in HCLK clock cycles, for reading data after CAS latency
CSDRAM_RowAddressBits	Enumeration for FMC SDRAM Row Address Bits These bits define the number of bits of a row address
CSDRAM_TimingStruct	FMC SDRAM Timing structure definition
CSDRAM_WriteProtection	Enumeration for FMC SDRAM Write Protection This bit enables write mode access to the SDRAM bank
►CGPIO	General Purpose I/O module Reference: ST_CortexM7_STM32F769_TRM_Rev2.pdf Chapter 6
CAlt	Enumeration for alternate function
CInitStruct	GPIO configuration structure definitions
CMode	Enumeration for GPIO Modi
COutputType	Enumeration for Output Type
CPin	Enumeration available GPIO Pins
CPinDefinitionStruct	Structur for PinDefinition
CPinEXTIDefinitionStruct	Structur for GPIO EXTI
CPinState	Enumeration identifiers of pin state
CPortMode	Enumeration for Port Modi
CPull	Enumeration for PinConfiguration
CSpeed	Enumeration for Output Speed
►CI2C	Inter-Integrated Circuit I2C module Reference: ST_CortexM7_STM32F769_TRM_Rev4.pdf Chapter 33
CAddressingMode	Enumeration for I2C Addressing Mode
CAutoend	Enumeration for I2C Autoend setting
CDigitalNoiseFilter	Enumeration for I2C Digital noise filter
CFlag	Enumeration for I2C for reading flags
CInitStruct
CIrqClear	Enumeration for I2C for clearing flags
CIrqEnable	Enumeration for I2C for enabling available interrupts
COwnAddress2Mask	Enumeration for I2C Own Address2 Masks
CTxRxStruct
CTxStruct
►CI2S	Inte-IC sound module
CAudioFrequency	Enumeration for the AudioFrequency
CDataformat	Enumeration for Data format
CI2SStandard	Enumeration for I2S standard selection
CInactiveClockPolarity	Enumeration for inactive state clock polarity
CInitStruct	I2S configuration structure definitions
CMasterClockOutput	Enumeration for Master clock output enable
CMode	Enumeration for I2S configuration mode
►CIWDG	Independent watchdog (IWDG) module Reference: ST_CortexM7_STM32F769_TRM_Rev2.pdf Chapter 30
CTimeOut	Enumeration for pre calculated timeouts
►CLTDC	LCD-TFT controller (LTDC) module register structure
CBackgroundColorStruct	Struct for the possible background Colors
CBlendingFactor1	Enumeration for blending factor1
CBlendingFactor2	Enumeration for blending factor2
CInitStruct	LTDC Init structure definition
CLayerConfigStruct	LTDC Layer structure definition
CPixelFormat	Enumeration for pixel format
CPolarity	Enumeration for the Polarity Options
►CMPU	Memory Protection Unit (MPU) Reference : ARM Cortex-M7 Generic User Guide DUI0646B.pdf Chapter 4.6 Optional Memory Protection Unit
CAccessPermission	Enumeration for MPU Region Permission Attributes
CControl	Enumeration for MPU Control
CInstructionAccess	Enumeration for MPU Instruction Access
CRegionConfigStruct	MPU Region structure definition
CRegionEnable	Enumeration for MPU Region Enable
CRegionNumber	Enumeration for MPU Region Number
CRegionSize	Enumeration for MPU Region Size Specifies the size of the MPU protection region
►CNVIC	Nested vectored interrupt controller (NVIC) peripheral module
CIrq	STM32F769 Interrupt Number Definition
CIrqPriority	STM32F769 has 4 priority bits (=0xF = 16 priorities)
►CPWR	Power controller module Reference: ST_CortexM7_STM32F769_TRM_Rev2.pdf Chapter 4
CBackupDomainAccess	Enumeration for Disable backup domain write protection, PWR_CR1.DBP
CFlashPowerDownInStopMode	Enumeration for flash power down in stop mode PWR_CR1.FPDS
CLowPowerDeepSleepMode	Enumeration for Low power deepsleep, PWR_CR1.LPDS
CLowPowerRegulatorDeepSleep	Enumeration for lpw power regulator in deep sleep under drive mode, PWR_CR1.LPUDS
CMainRegulatorDeepSleep	Enumeration for main regulator in deepsleep under drive mode, PWR_CR1.MRUDS
COverDriveEnable	Enumeration for for overdrive enabled, PWR_CR1.ODEN
COverDriveSwitchingEnable	Enumeration for for overdrive switching enabled, PWR_CR1.ODSWEN
CPowerDownDeepSleepMode	Enumeration for Power down deepsleep, PWR_CR1.PDDS
CPowerVoltageDetectorEnable	Enumeration for Power voltage detector enable, PWR_CR1.PVDE - not used
CStopModeConfigStruct	Stop Mode Configuration structure
CStopModeEntryMethod	Enumeration for stop mode entry method
CUnderDriveEnable	Enumeration for under drive enable in stop mode, PWR_CR1.UDEN
CVoltageScaling	Enumeration for regulator voltage scaling output selection, PWR_CR1.VOS
CWakeupPinEnable	Enumeration for Enable Pin Wakeup - not used
CWakeupPinPolarity	Enumeration for Wakeup pin polarity - not used
►CQSPI	(QSPI) module register structure
CAutomaticStop	Enumeration for QSPI Autopolling Automatic Stop
CAutoPollingInitStructure	QSPI AutoPolling structure definition
CByteSize	Enumeration for ByteSize
CChipSelectHighTime	Enumeration for Chip select high time
CCommandInitStruct	QSPI Command structure definition
CDataLines	Enumeration for LineNumbers
CDDR_HoldHalfCycle	Enumeration for QSPI DDR HoldHalfCycle
CDDR_ModeEnable	Enumeration for QSPI DDR Mode
CDDR_SIOO_Mode	Enumeration for QSPI DDR SIOOMode
CDualFlashModeEnable	Enumeration for Dual Flash Mode Enable
CFlashMemorySelection	Enumeration for Flash Memory Selection
CFunctionalMode	Enumeration for QSPI Functional Mode
CInitStruct	QSPI Init structure definition
CMatchMode	Enumeration for QSPI Autopolling MatchMode
CMemoryMapInitStructure	QSPI Memory Mapped mode structure definition
CMode	Enumeration for Mode Selection
CSampleShift	Enumeration for Sample shift
CTimeOutActivation	Enumeration for QSPI TimeOutActivation
►CRCC	Reset and clock control (RCC) peripheral module
CAHBClockDivider	Enumeration for AHB clock divider Chapter 5.3.3, RCC_CFGR Bits 7:4 HPRE
CAPB1APB2ClockDivider	Enumeration for APB1 and APB2 clock divider Chapter 5.3.3, RCC_CFGR Bits 7:4 PPRE1 AND Bits 12:10 PPRE1
CClockConfigStruct	RCC System, AHB and APB busses clock configuration structure
CDSIClockSource	Enumeration for DSI clock source
CI2CClockSource	I2C clock source selection
CI2SClockSource	Enumeration for I2S clock source
COscillatorConfigStruct	RCC Oscillator configuration structure definition
COscillatorState	Enumeration for OscillatorState
COscillatorType	Enumeration for Oscillator type
CPeripheralModule	Enumeration of all avalibale peripheral modules
CPLL	Enumeration for PLL Configuration
CPLLClockSource	Enumeration for PLL Clock Source Configuration Chapter 5.3.2, RCC_PLLCFGR Bit 22 PLLSRC
CPLLConfigStruct	PLL (phase locked loop) configuration structure definition
CPLLPClockDivider	Enumeration for PLLP Clock Divider Configuration Chapter 5.3.2, RCC_PLLCFGR Bits 17:16 PLLP[1:0]
CPllSaiDivR	PLLSAI division factor for LCD_CLK
CRTCSource	Enumeration for possible RTC sources
CSystemClockSource	Enumeration for system Clock Source Configuration Chapter 5.3.3, RCC_CFGR Bits 1:0 SW
CSystemClockType	Enumeration for system clock type Configuration
►CRTC	Real time Clock module Reference: ST_CortexM7_STM32F769_TRM_Rev2.pdf Chapter 32
CAMPM	Enumeration for AM/PM selection
CDateStruct	RTC time structure definitions
CDayLightSaving	Enumeration for Output selection - not used in current implementation
CHourFormat	Enumeration for hour format
CInitStruct	RTC config structure definition
CMonth	Enumeration for month day units
CTimeStruct	RTC time structure definitions
CWeekday	Enumeration for weekday units
►CSDMMC	SD/SDIO/MMC card host interface (SDMMC) Reference: ST_CortexM7_STM32F769_TRM_Rev4.pdf Chapter 39
CBusWidth
CCardCSD	Card Specific Data: CSD Register
CCardState	SD Card State enumeration structure
CClockDiv	Collection of useful clock SDMMC inerface dividers
►CContext	SD context enumeration
CFlag
CHandle
CInstance	Peripheral Handle
CPeriphClockConfig	SDMMC Clock Configuration Structure
CSdCardInfo	SD Card Information Structure definition
CState	SD State enumeration structure
CSupportedCard	SD Supported Memory Cards
CSupportedVersion	SD Supported Version
►CSDMMCTypes	Types for SD/SDIO/MMC card host interface (SDMMC) Reference: ST_CortexM7_STM32F769_TRM_Rev4.pdf Chapter 39
CError	SD Error status enumeration Structure definition
CResponseRegister	Response Register
►CSDMMCUtils	Low Level Utils for SD/SDIO/MMC card host interface (SDMMC) Reference: ST_CortexM7_STM32F769_TRM_Rev4.pdf Chapter 39
CAppCmd	Following commands are SD Card Specific commands
CAppCmdInit
CCmdIndex	SDMMC Commands Index
CCmdInit
CResponse	Response Type
►CSPI	Serial peripheral interface(SPI) module register structure
CBaudRateControl	Enumeration for baud rate control
CClockPhase	Enumeration for clock phase
CClockPolarity	Enumeration for clock polarity
CDataSize	Enumeration for data size
CFlag	Enumeration for available Flags
CFrameFormat	Enumeration for frame format
CInitStruct	SPI Init structure definition
CIrq	Enumeration for available interrupts
CMasterSelection	Enumeration for Master Slave Selection
CNssPulse	Enumeration for NSS Pulse
CSlaveSelect	Enumeration for slave management
CSlaveSelectOutput	Enumeration for MultiMasterMode
CSYSCFG	System Configuration Controller
CSYSTICK	System timer (SysTick) peripheral modul Reference: ARM Cortex-M7 Generic User Guide DUI0646B Chapter 4.4
►CTIM	Timer (TIMx) peripheral module
CAlignedMode	Enumeration of the available center aligned counter modes
CAutoReloadPreload	Enumeration of the available TIM AutoReload Preload parameters TIMx_CR1 Bit 7 ARPE
CChannel	Enumeration of the available TIM Complementary OC Pin State parameters
CClkSrcInitStruct	TIM clock init structure definition
CClockDivision	Enumeration of the available TIM ClockDivision parameters TIMx_CR1 Bits 9:8 CKD[1:0] This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock(tDTS)used by the dead-time generators and the digital filters
CClockPolarity	Enumeration of the available TIM Clock polarity parameters
CClockPrescaler	Enumeration of the available TIM Clock prescaler parameters
CClockSource	Enumeration of the available TIM Clock source parameters Note : Add other clock sources when implemented
CDirection	Enumeration of the available counter directions
CEncInitStruct	Encoder Configuration structure defintion
CEncoderMode	Enumeration of the available TIM EncoderMode parameters TIMx_SMCR Bits 2:0 SMS : Slave mode selection
CFlag	Enumeration of the available interrupt flags
CICInitStruct	Input Capture Configuration structure defintion
CICPolarity	Enumeration of the available TIM IC Polarity parameters TIMx_CCER Bit 1 CCxP and Bit 3 CCxNP CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations
CICPrescaler	Enumeration of the available TIM Prescaler parameters IC1PSC This bit - field defines the ratio of the prescaler acting on CC1 input(IC1)
CICSelection	Enumeration of the available TIM IC Selection parameters Bits CCxS : Capture / Compare selection This bit - field defines the direction of the channel(input / output) as well as the used input
CInitStruct	TIM Init structure definition
CIrq	Enumeration of the available interrupts
CMasterInitStruct	Master Configuration structure defintion
CMasterOutputTrigger	Enumeration of the available Trigger Output parameters TIMx_CR2 Bits 6:4 MMS[2:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization(TRGO)
CMasterOutputTrigger2	Enumeration of the available Trigger Output parameters TIMx_CR2 Bits 23:20 MMS2[3:0]: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization(TRGO2) to be selected
CMasterSlaveMode	Enumeration of the available MasterSlave Mode parameters TIMx_SMCR Bit 7 MSM: Master / Slave mode
COCFastMode	Enumeration of the available TIM OC Fast Mode parameters
COCIdleState	Enumeration of the available TIM OC Pin State parameters
COCInitStruct	Output Compare configuration structure definition
COCMode	Enumeration of the available TIM OC Mode TIMx_CCMRx Bits OCxM These bits define the behavior of the output reference signal
COCNIdleState	Enumeration of the available TIM Complementary OC Pin State parameters
COCNPolarity	Enumeration of the available TIM Complementary OC polarity parameters
COCPolarity	Enumeration of the available TIM OC polarity parameters
CSlaveInitStruct	Slave configuration structure
CSlaveMode	Enumeration of the available slave mode parameters
CTriggerInput	Enumeration of the available trigger input parameters
CTriggerPolarity	Enumeration of the available trigger polarity parameters
CTriggerPrescaler	Enumeration of the available trigger prescaler parameters
►CUSART	Usart/Uart peripheral module Reference: ST_CortexM7_STM32F769_TRM_Rev2.pdf Chapter 34
CAutoBaudRateMode	Enumeration for Auto Baud Rate Mode - not used in current implementation
CBaudrate	Enumeration the Baud Value and its BRR Value for OverSampling 8
CHardwareFlowControl	Enumeration for the Hardware Flow Control Options
CInitStruct	Usart Init structure definition
CInterrupt	Enumeration of avaiable interrupts on the usart/uart module
COneBitSampling	Enumeration of on bit sampling modes
COverSamplingMode	Enumeration for Oversampling Mode
CParity	Enumeration for the parity options
CStopBit	Enumeration for Stop bit
CTransferMode	Enumeration for Stop bit
CWordLength	Enumeration for the Word Length
►CUsbHost	USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) Host implementation Reference: ST_CortexM7_STM32F769_TRM_Rev4.pdf Chapter 41
CHandle	HCD Handle Structure definition
CState	HostControlDriver State Structure
►CUsbTypes	Types for USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) Reference: ST_CortexM7_STM32F769_TRM_Rev4.pdf Chapter 41
CDataPid	DataPid
ChChConfig	Host channel configuration
CHcState	Host channel States definition
CUrbState	URB States definition
CUsbConfig
CUsbEpType	USB End Point Type,
CUsbMode	USB Mode
CUsbPhy	USB Phy
CUsbPhyClock	USB Low Layer HCFG Speed
CUsbPortSpeed	USB Port Speed
CUsbUtils	Low Level Utils for USB interface Reference: ST_CortexM7_STM32F769_TRM_Rev4.pdf Chapter 41
►Nregisters
►CADCCommonRegisters	ADC Common module (ADCCOMMON) register structure
CADC_CCR	ADC common control register (ADC_CCR), chapter 15.13.16
CADC_CDR	ADC common regular data register for dual and triple modes (ADC_CDR), chapter 15.13.17
CADC_CSR	ADC Common status register (ADC_CSR), chapter 15.13.15
►CADCRegisters	Analog digital converter (ADC) register structure
►CADC_CR1	ADC control register 1 (ADC_CR1), chapter 15.13.2
CFields
►CADC_CR2	ADC control register 2 (ADC_CR2), chapter 15.13.3
CFields
CADC_DR	ADC reguler data register (ADC_DR), chapter 15.13.14
CADC_HTR	ADC watchdog higher threshold register (ADC_HTR), chapter 15.13.7
CADC_JDRx	ADC injected data register x (ADC_JDRx) (x= 1..4), chapter 15.13.13
CADC_JOFRx	ADC injected channel data offset register x (ADC_JOFRx) (x=1..4), chapter 15.13.6
CADC_JSQR	ADC injected sequence register (ADC_JSQR), chapter 15.13.12
CADC_LTR	ADC watchdog lower threshold register (ADC_LTR), chapter 15.13.8
CADC_SMPR1	ADC sample time register 1 (ADC_SMPR1), chapter 15.13.4
CADC_SMPR2	ADC sample time register 2 (ADC_SMPR2), chapter 15.13.5
CADC_SQR1	ADC regular sequence register 1 (ADC_SQR1), chapter 15.13.9
CADC_SQR2	ADC regular sequence register 2 (ADC_SQR2), chapter 15.13.10
CADC_SQR3	ADC regular sequence register 3 (ADC_SQR3), chapter 15.13.11
►CADC_SR	ADC status register (ADC_SR), chapter 15.13.1
CFields
►CCANRegisters	Controller area network(CAN) module register structure
CCAN_BTR	CAN bit timing register (CAN_BTR), chapter 40.9.2
CCAN_ESR	CAN error status register (CAN_ESR), chapter 40.9.2
CCAN_FA1R	CAN filter activation register (CAN_FA1R), chapter 40.9.3
CCAN_FFA1R	CAN filter FIFO assignment register (CAN_FFA1R), chapter 40.9.3
CCAN_FIFOMailbox	CAN FIFO mailbox register set (CAN_FIFOMailbox), chapter 40.9.3
CCAN_FiR	CAN filter Filter bank i register x (CAN_FiRx) (i=0..27, x=1..2), chapter 40.9.3
CCAN_FM1R	CAN filter mode register (CAN_FM1R), chapter 40.9.3
CCAN_FMR	CAN filter master register (CAN_FMR), chapter 40.9.3
CCAN_FS1R	CAN filter scale register (CAN_FS1R), chapter 40.9.3
CCAN_IER	CAN interrupt enable register (CAN_IER), chapter 40.9.2
CCAN_MCR	CAN master control register (CAN_MCR), chapter 40.9.2
CCAN_MSR	CAN master status register (CAN_MSR), chapter 40.9.2
CCAN_RDHxR	CAN receive FIFO mailbox data high register (CAN_RDHxR) (x=0..1), chapter 40.9.3
CCAN_RDLxR	CAN receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1), chapter 40.9.3
CCAN_RDTxR	CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x=0..1), chapter 40.9.3
CCAN_RF0R	CAN receive FIFO 0 register (CAN_RF0R), chapter 40.9.2
CCAN_RF1R	CAN receive FIFO 1 register (CAN_RF1R), chapter 40.9.2
CCAN_RIxR	CAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1), chapter 40.9.3
CCAN_TDHxR	CAN mailbox data HIGH register (CAN_TDHxR) (x=0..2), chapter 40.9.3
CCAN_TDLxR	CAN mailbox data low register (CAN_TDLxR) (x=0..2), chapter 40.9.3
CCAN_TDTxR	CAN mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2), chapter 40.9.3
CCAN_TIxR	CAN TX mailbox identifier register (CAN_TIxR) (x=0..2), chapter 40.9.3
CCAN_TSR	CAN transmit status register (CAN_TSR), chapter 40.9.2
CCAN_TxMailbox	CAN tx mailbox register set (CAN_TxMailbox), chapter 40.9.3
►CCRCRegisters	(CRC) module register structure
CCRC_CR	Control register (CRC_CR), chapter 12.4.3
CCRC_DR	Data register (CRC_DR), chapter 12.4.1
CCRC_IDR	Independent data register (CRC_IDR), chapter 12.4.2
CCRC_INIT	Initial CRC value (CRC_INIT), chapter 12.4.4
CCRC_POL	CRC polynomial (CRC_POL), chapter 12.4.5
►CDACRegisters	Digital to Analog Converter(DAC) module register structure
CDAC_CR	DAC control register (DAC_CR), chapter 16.5.1
CDAC_DHR12L1	DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1), chapter 16.5.4
CDAC_DHR12L2	DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2), chapter 16.5.7
CDAC_DHR12LD	DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), chapter 16.5.10
CDAC_DHR12R1	DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1), chapter 16.5.3
CDAC_DHR12R2	DAC channel2 12-bit right-aligned data holding register (DAC_DHR12R2), chapter 16.5.6
CDAC_DHR12RD	Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), chapter 16.5.9
CDAC_DHR8R1	DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1), chapter 16.5.5
CDAC_DHR8R2	DAC channel2 8-bit right aligned data holding register (DAC_DHR8R2), chapter 16.5.8
CDAC_DHR8RD	DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), chapter 16.5.11
CDAC_DOR1	DAC channel1 data output register (DAC_DOR1), chapter 16.5.12
CDAC_DOR2	DAC channel2 data output register (DAC_DOR2), chapter 16.5.13
CDAC_SR	DAC status register (DAC_SR), chapter 16.5.14
CDAC_SWTRIGR	DAC software trigger register (DAC_SWTRIGR), chapter 16.5.2
►CDBGRegisters	Debug support (DBG)
►CDBGMCU_APB1_FZ	44.16.5 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
CFields
►CDBGMCU_APB2_FZ	44.16.6 Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ)
CFields
►CDBGMCU_CR	44.16.4 DBGMCU_CR register
CFields
►CDBGMCU_IDCODE	44.6.1 MCU device ID code DBGMCU_IDCODE
CFields
►CDMA2DRegisters	Chrom-art Accelerator (DMA2D) module register structure
CDMA2D_AMTCR	DMA2D AHB master timer configuration register (DMA2D_AMTCR), chapter 9.5.20
CDMA2D_BGCMAR	DMA2D background CLUT memory address register (DMA2D_BGCMAR), chapter 9.5.13
CDMA2D_BGMAR	DMA2D background memory address register (DMA2D_BGMAR), chapter 9.5.6
►CDMA2D_CR	DMA2D control register (DMA2D_CR), chapter 9.5.1
CFields
CDMA2D_FGCMAR	DMA2D foreground CLUT memory address register (DMA2D_FGCMAR), chapter 9.5.12
►CDMA2D_FGCOLR	DMA2D foreground/background color register (DMA2D_FGCOLR), chapter 9.5.9
CFields
CDMA2D_FGMAR	DMA2D foreground memory address register (DMA2D_FGMAR), chapter 9.5.4
CDMA2D_FGOR	DMA2D foreground/background offset register (DMA2D_FGOR), chapter 9.5.5
►CDMA2D_FGPFCCR	DMA2D foreground/background PFC control register (DMA2D_FGPFCCR), chapter 9.5.8
CFields
►CDMA2D_IFCR	DMA2D interrupt flag clear register (DMA2D_IFCR), chapter 9.5.3
CFields
CDMA2D_ISR	DMA2D Interrupt Status Register (DMA2D_ISR), chapter 9.5.2
CDMA2D_LWR	DMA2D line watermark register (DMA2D_LWR), chapter 9.5.19
►CDMA2D_NLR	DMA2D number of line register (DMA2D_NLR), chapter 9.5.18
CBitField
►CDMA2D_OCOLR	DMA2D output color register (DMA2D_OCOLR), chapter 9.5.15
►CARGB1555
CFields
►CARGB4444
CFields
►CARGB888
CFields
►CRGB565
CFields
►CRGB888
CFields
CDMA2D_OMAR	DMA2D output memory address register (DMA2D_OMAR), chapter 9.5.16
CDMA2D_OOR	DMA2D output offset register (DMA2D_OOR), chapter 9.5.17
►CDMA2D_OPFCCR	DMA2D output PFC control register (DMA2D_OPFCCR), chapter 9.5.14
CFields
►CDMARegisters	Direct memory access (DMA) register structure
CDMA_HIFCR	DMA low interrupt flag clear register (DMA_HIFCR), chapter 8.5.4
CDMA_HISR	DMA high interrupt status register (DMA_HISR), chapter 8.5.2
CDMA_LIFCR	DMA low interrupt flag clear register (DMA_LIFCR), chapter 8.5.3
CDMA_LISR	DMA low interrupt status register (DMA_LISR), chapter 8.5.1
►CDMAStreamRegisters	Direct memory access (DMA) stream register structure
CDMA_SxCR	DMA stream x configuration register (DMA_SxCR) (x = 0..7), chapter 8.5.5
CDMA_SxFCR	DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7), chapter 8.5.10
CDMA_SxM0AR	DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7), chapter 8.5.8
CDMA_SxM1AR	DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7), chapter 8.5.9
CDMA_SxNDTR	DMA stream x number of data register (DMA_SxNDTR) (x = 0..7), chapter 8.5.6
CDMA_SxPAR	DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7), chapter 8.5.7
►CDSIRegisters	DSI host controller (DSI) module register structure
CDSI_CCR	DSI Host Clock Control Register (DSI_CCR), chapter 20.15.3
CDSI_CLCR	DSI Host Clock Lane Configuration Register (DSI_CLCR), chapter 20.15.33
CDSI_CLTCR	DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR), chapter 20.15.34
CDSI_CMCR	DSI Host Command mode Configuration Register (DSI_CMCR), chapter 20.15.23
CDSI_CR	DSI Host Control Register (DSI_CR), chapter 20.15.2
CDSI_DLTCR	DSI Host Data Lane Timer Configuration Register (DSI_DLTCR), chapter 20.15.35
CDSI_FIR0	DSI Host Force Interrupt Register 0 (DSI_FIR0), chapter 20.15.45
CDSI_FIR1	DSI Host Force Interrupt Register 1 (DSI_FIR1), chapter 20.15.46
►CDSI_GHCR	DSI Host Generic Header Configuration Register (DSI_GHCR), chapter 20.15.24
CFields
►CDSI_GPDR	DSI Host Generic Payload Data Register (DSI_GPDR), chapter 20.15.25
CFields
►CDSI_GPSR	DSI Host Generic Packet Status Register (DSI_GPSR), chapter 20.15.26
CFields
CDSI_GVCIDR	DSI Host Generic VCID Register (DSI_GVCIDR), chapter 20.15.9
►CDSI_IER0	DSI Host Interrupt Enable Register 0 (DSI_IER0), chapter 20.15.43
CBits
CFields
►CDSI_IER1	DSI Host Interrupt Enable Register 1 (DSI_IER1), chapter 20.15.44
CFields
►CDSI_ISR0	DSI Host Interrupt & Status Register 0 (DSI_ISR0), chapter 20.15.41
CBits
CFields
►CDSI_ISR1	DSI Host Interrupt & Status Register 1 (DSI_ISR1), chapter 20.15.42
CBits
CDSI_LCCCR	DSI Host LTDC Current Color Coding Register (DSI_LCCCR), chapter 20.15.49
CDSI_LCCR	DSI Host LTDC Command Configuration Register (DSI_LCCR), chapter 20.15.22
CDSI_LCOLCR	DSI Host LTDC Color Coding Register (DSI_LCOLCR), chapter 20.15.5
CDSI_LCVCIDR	DSI Host LTDC Current VCID Register (DSI_LCVCIDR), chapter 20.15.48
CDSI_LPCR	DSI Host LTDC Polarity Configuration Register (DSI_LPCR), chapter 20.15.6
CDSI_LPMCCR	DSI Host Low-Power mode Current Configuration Register (DSI_LPMCCR), chapter 20.15.50
CDSI_LPMCR	DSI Host Low-Power mode Configuration Register (DSI_LPMCR), chapter 20.15.7
CDSI_LVCIDR	DSI Host LTDC VCID Register (DSI_LVCIDR), chapter 20.15.4
CDSI_MCR	DSI Host mode Configuration Register (DSI_MCR), chapter 20.15.10
CDSI_PCONFR	DSI Host PHY Configuration Register (DSI_PCONFR), chapter 20.15.37
►CDSI_PCR	DSI Host Protocol Configuration Register (DSI_PCR), chapter 20.15.8
CBits
CDSI_PCTLR	DSI Host PHY Control Register (DSI_PCTLR), chapter 20.15.36
CDSI_PSR	DSI Host PHY Status Register (DSI_PSR), chapter 20.15.40
CDSI_PTTCR	DSI Host PHY TX Triggers Configuration Register (DSI_PTTCR), chapter 20.15.39
►CDSI_PUCR	DSI Host PHY ULPS Control Register (DSI_PUCR), chapter 20.15.38
CBits
CDSI_TCCR0	DSI Host Timeout Counter Configuration Register 0 (DSI_TCCR0), chapter 20.15.27
CDSI_TCCR1	DSI Host Timeout Counter Configuration Register 1 (DSI_TCCR1), chapter 20.15.28
CDSI_TCCR2	DSI Host Timeout Counter Configuration Register 2 (DSI_TCCR2), chapter 20.15.29
CDSI_TCCR3	DSI Host Timeout Counter Configuration Register 3 (DSI_TCCR3), chapter 20.15.30
CDSI_TCCR4	DSI Host Timeout Counter Configuration Register 4 (DSI_TCCR4), chapter 20.15.31
CDSI_TCCR5	DSI Host Timeout Counter Configuration Register 5 (DSI_TCCR5), chapter 20.15.32
CDSI_TDCCR	DSI Host Register (DSI_TDCCR), not documented in TRM Rev4, information from QubeMx Example HAL
CDSI_TDCR	DSI Host Register DSI_TDCR), not documented in TRM Rev4, information from QubeMx Example HAL
CDSI_VCCCR	DSI Host Video Chunks Current Configuration Register (DSI_VCCCR), chapter 20.15.53
CDSI_VCCR	DSI Host Video Chunks Configuration Register (DSI_VCCR), chapter 20.15.13
CDSI_VHBPCCR	DSI Host Video HBP Current Configuration Register (DSI_VHBPCCR), chapter 20.15.56
CDSI_VHBPCR	DSI Host Video HBP Configuration Register (DSI_VHBPCR), chapter 20.15.16
CDSI_VHSACCR	DSI Host Video HSA Current Configuration Register (DSI_VHSACCR), chapter 20.15.55
CDSI_VHSACR	DSI Host Video HSA Configuration Register (DSI_VHSACR), chapter 20.15.15
CDSI_VLCCR	DSI Host Video Line Current Configuration Register (DSI_VLCCR), chapter 20.15.57
CDSI_VLCR	DSI Host Video Line Configuration Register (DSI_VLCR), chapter 20.15.17
CDSI_VMCCR	DSI Host Video mode Current Configuration Register (DSI_VMCCR), chapter 20.15.51
CDSI_VMCR	DSI Host Video mode Configuration Register (DSI_VMCR), chapter 20.15.11
CDSI_VNPCCR	DSI Host Video Null Packet Current Configuration Register (DSI_VNPCCR), chapter 20.15.54
CDSI_VNPCR	DSI Host Video Null Packet Configuration Register (DSI_VNPCR), chapter 20.15.14
CDSI_VPCCR	DSI Host Video Packet Current Configuration Register (DSI_VPCCR), chapter 20.15.52
CDSI_VPCR	DSI Host Video Packet Configuration Register (DSI_VPCR), chapter 20.15.12
CDSI_VSCR	DSI Host Video Shadow Control Register (DSI_VSCR), chapter 20.15.47
CDSI_VVACCR	DSI Host Video VA Current Configuration Register (DSI_VVACCR), chapter 20.15.61
CDSI_VVACR	DSI Host Video VA Configuration Register (DSI_VVACR), chapter 20.15.21
CDSI_VVBPCCR	DSI Host Video VBP Current Configuration Register (DSI_VVBPCCR), chapter 20.15.59
CDSI_VVBPCR	DSI Host Video VBP Configuration Register (DSI_VVBPCR), chapter 20.15.19
CDSI_VVFPCCR	DSI Host Video VFP Current Configuration Register (DSI_VVFPCCR), chapter 20.15.60
CDSI_VVFPCR	DSI Host Video VFP Configuration Register (DSI_VVFPCR), chapter 20.15.20
CDSI_VVSACCR	DSI Host Video VSA Current Configuration Register (DSI_VVSACCR), chapter 20.15.58
CDSI_VVSACR	DSI Host Video VSA Configuration Register (DSI_VVSACR), chapter 20.15.18
CDSI_WCFGR	20.16 DSI Wrapper Registers
CDSI_WCR	DSI Wrapper Control Register (DSI_WCR), chapter 20.16.2
CDSI_WIER	DSI Wrapper Interrupt Enable Register (DSI_WIER), chapter 20.16.3
CDSI_WIFCR	DSI Wrapper Interrupt Flag Clear Register (DSI_WIFCR), chapter 20.16.5
CDSI_WISR	DSI Wrapper Interrupt & Status Register (DSI_WISR), chapter 20.16.4
CDSI_WPCR0	DSI Wrapper PHY Configuration Register 0 (DSI_WPCR0), chapter 20.16.6
CDSI_WPCR1	DSI Wrapper PHY Configuration Register 1 (DSI_WPCR1), chapter 20.16.7
CDSI_WPCR2	DSI Wrapper PHY Configuration Register 2 (DSI_WPCR2), chapter 20.16.8
CDSI_WPCR3	DSI Wrapper PHY Configuration Register 3 (DSI_WPCR3), chapter 20.16.9
CDSI_WPCR4	DSI Wrapper PHY Configuration Register 4 (DSI_WPCR4), chapter 20.16.10
CDSI_WRPCR	DSI Wrapper Regulator and PLL Control Register (DSI_WRPCR), chapter 20.16.11
►CEXTIRegisters	(EXTI) module register structure
CEXTI_x	EXT_x register (EXTI_IMR, EXTI_EMR, EXTI_RTSR, EXTI_FTSR, EXTI_SWIER, EXTI_PR), chapter 11.9.1 to 6
►CFLASHRegisters	Flash (FLASH) registers
CFLASH_ACR	FLASH Access Control Register Access: no wait state, word, half-word and byte access
CFLASH_CR	FLASH control register Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_KEYR	FLASH Key register Access: no wait state, word access
CFLASH_OPTCR	FLASH option control register Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_OPTCR1	FLASH option control register 1 Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_OPTKEYR	FLASH Option key register Access: no wait state, word access
CFLASH_SR	FLASH status register Access: no wait state, word, half-word and byte access
►CFMCRegisters	(FMC) module register structure
CFMC_BCR	SRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4), chapter 13.5.6
CFMC_BTR	SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4), chapter 13.5.6
CFMC_BWTR	SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4), chapter 13.5.6
CFMC_ECCR	ECC result registers (FMC_ECCR), chapter 13.6.7
CFMC_PATT	Attribute memory space timing registers (FMC_PATT), chapter 13.6.7
CFMC_PCR	NAND Flash control registers(FMC_PCR), chapter 13.6.7
CFMC_PMEM	Common memory space timing register 2..4 (FMC_PMEM), chapter 13.6.7
►CFMC_SDCMR	SDRAM Command Mode register (FMC_SDCMR), chapter 13.6.7
CFields
CFMC_SDCRx	SDRAM Control registers 1,2 (FMC_SDCR1,2), chapter 13.7.5
CFMC_SDRTR	SDRAM Refresh Timer register (FMC_SDRTR), chapter 13.6.7
CFMC_SDSR	SDRAM Status register (FMC_SDSR), chapter 13.6.7
CFMC_SDTR	SDRAM Timing registers 1,2 (FMC_SDTR1,2), chapter 13.7.5
CFMC_SR	FIFO status and interrupt register (FMC_SR), chapter 13.6.7
►CGPIORegisters	General purpose input/output module (GPIO) register structure
CGPIOx_AFRH	GPIO alternate function high register (GPIOx_AFRH) (x = A..K), chapter 6.4.10
CGPIOx_AFRL	GPIO alternate function low register (GPIOx_AFRL) (x = A..K), chapter 6.4.9
CGPIOx_BSRR	GPIO port bit set/reset register (GPIOx_BSRR) (x = A..K), chapter 6.4.7
CGPIOx_IDR	GPIO port input data register (GPIOx_IDR) (x = A..K), chapter 6.4.5
CGPIOx_MODER	GPIO port mode register (GPIOx_MODER) (x =A..K), chapter 6.4.1
CGPIOx_ODR	GPIO port output data register (GPIOx_ODR) (x = A..K), chapter 6.4.6
CGPIOx_OSPEEDR	GPIO port output speed register (GPIOx_OSPEEDR) (x = A..K), chapter 6.4.3
CGPIOx_OTYPER	GPIO port output type register (GPIOx_OTYPER) (x = A..K), chapter 6.4.2
CGPIOx_PUPDR	GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..K), chapter 6.4.4
►CI2CRegisters	(IC2) module register structure
CI2C_CR1	Control register 1 (I2C_CR1), chapter 33.7.1
CI2C_CR2	Control register 2 (I2C_CR2), chapter 33.7.2
CI2C_ICR	Interrupt clear register (I2C_ICR), chapter 33.7.8
CI2C_ISR	Interrupt and status register (I2C_ISR), chapter 33.7.7
►CI2C_OAR1	Own address 1 register (I2C_OAR1), chapter 33.7.3
CAddressMode10Bit
CAddressMode7Bit
CI2C_OAR2	Own address 2 register (I2C_OAR2), chapter 33.7.4
CI2C_PECR	PEC register (I2C_PECR), chapter 33.7.9
CI2C_RXDR	Receive data register (RXDR_RXDR), chapter 33.7.10
CI2C_TIMEOUTR	Timeout register (I2C_TIMEOUTR), chapter 33.7.6
CI2C_TIMINGR	Timing register (I2C_TIMINGR), chapter 33.7.5
CI2C_TXDR	Transmit data register (I2C_TXDR), chapter 33.7.11
►CI2SRegisters	Inter IC Sound (I2S) module register structure
CSPIx_CR1	SPI control register 1 (SPIx_CR1), chapter 35.9.1
CSPIx_CR2	SPI control register 2 (SPIx_CR2), chapter 35.9.2
CSPIx_CRCPR	SPI CRC polynomial register (SPIx_CRCPR) , chapter 35.9.5
CSPIx_DR	SPI data register (SPIx_DR), chapter 35.9.4
CSPIx_I2SCFGR	SPIx_I2S configuration register (SPIx_I2SCFGR), chapter 35.9.8
CSPIx_I2SPR	SPIx_I2S prescaler register (SPIx_I2SPR), chapter 35.9.9
CSPIx_RXCRCR	SPI Rx CRC register (SPIx_RXCRCR) , chapter 35.9.7
CSPIx_SR	SPI status register (SPIx_SR), chapter 35.9.3
CSPIx_TXCRCR	SPI Tx CRC register (SPIx_TXCRCR) , chapter 35.9.8
►CIWDGRegisters	Independent watchdog module register (IWDG) structure
►CIWDG_KR	Key register (IWDG_KR), chapter 30.4.1
CFields
CIWDG_PR	Prescaler register (IWDG_PR), chapter 30.4.2
CIWDG_RLR	Reload register (IWDG_RLR), chapter 30.4.3
CIWDG_SR	Status register (IWDG_SR), chapter 30.4.4
CIWDG_WINR	Window register (IWDG_WINR), chapter 30.4.5
►CLTDCLayerRegisters	LCD-TFT controller (LTDC) layer module register structure
►CLTDC_LxBFCR	LTDC layer x blending factors configuration register (LTDC_LxBFCR), chapter 19.7.21
CFields
CLTDC_LxCACR	LTDC layer x constant alpha configuration register (LTDC_LxCACR), chapter 19.7.19
CLTDC_LxCFBAR	LTDC layer x color frame buffer address register (LTDC_LxCFBAR), chapter 19.7.22
CLTDC_LxCFBLNR	LTDC layer x color frame buffer line number register (LTDC_LxCFBLNR), chapter 19.7.24
►CLTDC_LxCFBLR	LTDC layer x color frame buffer length register (LTDC_LxCFBLR), chapter 19.7.23
CFields
►CLTDC_LxCKCR	LTDC layer x color keying configuration register (LTDC_LxCKCR), chapter 19.7.17
CFields
►CLTDC_LxCLUTWR	LTDC layer x CLUT write register (LTDC_LxCLUTWR), chapter 19.7.25
CFields
CLTDC_LxCR	LTDC layer x control register (LTDC_LxCR), chapter 19.7.14
►CLTDC_LxDCCR	LTDC layer x default color configuration register (LTDC_LxDCCR), chapter 19.7.20
CFields
CLTDC_LxPFCR	LTDC layer x pixel format configuration register (LTDC_LxPFCR), chapter 19.7.18
►CLTDC_LxWHPCR	LTDC layer x window horizontal position configuration register (LTDC_LxWHPCR), chapter 19.7.15
CFields
►CLTDC_LxWVPCR	LTDC layer x window vertical position configuration register (LTDC_LxWVPCR), chapter 19.7.16
CFields
►CLTDCRegisters	LCD-TFT controller (LTDC) module register structure
►CLTDC_AWCR	LTDC active width configuration register (LTDC_AWCR), chapter 19.7.3
CFields
CLTDC_BCCR	LTDC background color configuration register (LTDC_BCCR), chapter 19.7.7
►CLTDC_BPCR	LTDC back porch configuration register (LTDC_BPCR), chapter 19.7.2
CFields
CLTDC_CDSR	LTDC current display status register (LTDC_CDSR), chapter 19.7.13
CLTDC_CPSR	LTDC current position status register (LTDC_CPSR), chapter 19.7.12
CLTDC_GCR	LTDC global control register (LTDC_GCR), chapter 19.7.5
CLTDC_ICR	LTDC Interrupt Clear Register (LTDC_ICR), chapter 19.7.10
►CLTDC_IER	LTDC interrupt enable register (LTDC_IER), chapter 19.7.8
CFields
CLTDC_ISR	LTDC interrupt status register (LTDC_ISR), chapter 19.7.9
CLTDC_LIPCR	LTDC line interrupt position configuration register (LTDC_LIPCR), chapter 19.7.11
CLTDC_SRCR	LTDC shadow reload configuration register (LTDC_SRCR), chapter 19.7.6
CLTDC_SSCR	LTDC Synchronization Size Configuration Register (LTDC_SSCR), chapter 19.7.1
CLTDC_TWCR	LTDC total width configuration register (LTDC_TWCR), chapter 19.7.4
►CMPURegisters	(MPU) register structure - Memory Protection Unit
CMPU_CTRL	MPU Control Register, Chapter 4.6.2
CMPU_RASR	MPU Region Attribute and Size Register, Chapter 4.6.5 Access: word access
CMPU_RBAR	MPU Region Base Address Register, Chapter 4.6.4
CMPU_RNR	MPU Region Number Register, Chapter 4.6.3
CMPU_TYPE	MPU Type Register, Chapter 4.6.1 The MPU_TYPE register indicates whether the optional MPU is present, and if so, how many regions it supports
►CNVICRegisters	(NVIC) register structure
CNVIC_STIR	Software Trigger Interrupt Register (NVIC_STIR), chapter 4.2.8, page 4-8
►CPWRRegisters	(PWR) register structure
CPWR_CR1	PWR power control register (PWR_CR1), chapter 4.4.1
CPWR_CR2	PWR power control/status register 2 (PWR_CR2) (PWR_CR2), chapter 4.4.3
CPWR_CSR1	PWR power control/status register (PWR_CSR1), chapter 4.4.2
CPWR_CSR2	PWR power control register 2 (PWR_CSR2), chapter 4.4.4
►CQSPIRegisters	(QSPI) module register structure
CQUADSPI_ABR	QUADSPI alternate bytes registers (QUADSPI_ABR), chapter 14.5.8
CQUADSPI_AR	QUADSPI address register (QUADSPI_AR), chapter 14.5.7
►CQUADSPI_CCR	QUADSPI communication configuration register (QUADSPI_CCR), chapter 14.5.6
CFields
CQUADSPI_CR	QUADSPI control register (QUADSPI_CR), chapter 14.5.1
CQUADSPI_DCR	QUADSPI device configuration register (QUADSPI_DCR), chapter 14.5.2
CQUADSPI_DLR	QUADSPI data length register (QUADSPI_DLR), chapter 14.5.5
CQUADSPI_DR	QUADSPI data register (QUADSPI_DR), chapter 14.5.9
CQUADSPI_FCR	QUADSPI flag clear register (QUADSPI_FCR), chapter 14.5.4
CQUADSPI_LPTR	QUADSPI low-power timeout register (QUADSPI_LPTR), chapter 14.5.13
CQUADSPI_PIR	QUADSPI polling interval register (QUADSPI_PIR), chapter 14.5.12
CQUADSPI_PSMAR	QUADSPI polling status match register (QUADSPI_PSMAR), chapter 14.5.11
CQUADSPI_PSMKR	QUADSPI polling status mask register (QUADSPI_PSMKR), chapter 14.5.10
CQUADSPI_SR	QUADSPI status register (QUADSPI_SR), chapter 14.5.3
►CRCCRegisters	(RCC) register structure
CRCC_AHB1ENR	RCC AHB1 peripheral clock register (RCC_AHB1ENR)), chapter 5.3.10 Access: no wait state, word, half-word and byte access
CRCC_AHB1LPENR	RCC AHB1 peripheral clock enable in low-power mode register (RCC_AHB1LPENR), chapter 5.3.15 Access: no wait state, word, half-word and byte access
CRCC_AHB1RSTR	RCC AHB1 peripheral reset register (RCC_AHB1RSTR), chapter 5.3.5 Access: no wait state, word, half-word and byte access
CRCC_AHB2ENR	RCC AHB2 peripheral clock enable register (RCC_AHB2ENR), chapter 5.3.11
CRCC_AHB2LPENR	RCC AHB2 peripheral clock enable in low-power mode register (RCC_AHB2LPENR), chapter 5.3.16 Access: no wait state, word, half-word and byte access
CRCC_AHB2RSTR	RCC AHB2 peripheral reset register (RCC_AHB2RSTR), chapter 5.3.6 Access: no wait state, word, half-word and byte access
CRCC_AHB3ENR	RCC AHB3 peripheral clock enable register (RCC_AHB2ENR), chapter 5.3.12 Access: no wait state, word, half-word and byte access
CRCC_AHB3LPENR	RCC AHB3 peripheral clock enable in low-power mode register (RCC_AHB3LPENR), chapter 5.3.17 Access: no wait state, word, half-word and byte access
CRCC_AHB3RSTR	RCC AHB3 peripheral reset register (RCC_AHB3RSTR), chapter 5.3.7 Access: no wait state, word, half-word and byte access
CRCC_APB1ENR	RRCC APB1 peripheral clock enable register (RCC_APB1ENR), chapter 5.3.13 Access: no wait state, word, half-word and byte access
CRCC_APB1LPENR	RCC APB1 peripheral clock enable in low-power mode register (RCC_APB1LPENR), chapter 5.3.18 Access: no wait state, word, half-word and byte access
CRCC_APB1RSTR	RCC APB1 peripheral reset register (RCC_APB1RSTR), chapter 5.3.8 Access: no wait state, word, half-word and byte access
CRCC_APB2ENR	RCC APB2 peripheral clock enable register (RCC_APB2ENR), chapter 5.3.14 Access: no wait state, word, half-word and byte access
CRCC_APB2LPENR	RCC APB2 peripheral clock enable in low-power mode register (RCC_APB2LPENR), chapter 5.3.19 Access: no wait state, word, half-word and byte access
CRCC_APB2RSTR	RCC APB2 peripheral reset register (RCC_APB2RSTR), chapter 5.3.9 Access: no wait state, word, half-word and byte access
CRCC_BDCR	RCC backup domain control register (RCC_BDCR), chapter 5.3.20 Access: 0 <= wait state <= 3, word, half-word and byte access
CRCC_CFGR	RCC clock configuration register (RCC_CFGR), chapter 5.3
CRCC_CIR	RCC clock interrupt register (RCC_CIR), chapter 5.3.4 Access: no wait state, word, half-word and byte access
CRCC_CR	RCC clock control register (RCC_CR), chapter 5.3.1 Access: no wait state, word, half-word and byte access
CRCC_CSR	RCC clock control & status register (RCC_CSR), chapter 5.3.21 Access: 0 <= wait state <= 3, word, half-word and byte access
CRCC_DCKCFGR1	RCC dedicated clocks configuration register (RCC_DCKCFGR1), chapter 5.3.25 Access: no wait state, word, half-word and byte access
CRCC_DCKCFGR2	RCC dedicated clocks configuration register (RCC_DCKCFGR2), chapter 5.3.26 Access: no wait state, word, half-word and byte access
CRCC_PLLCFGR	RCC PLL configuration register (RCC_PLLCFGR), chapter 5.3.2 Access: no wait state, word, half-word and byte access
CRCC_PLLI2SCFGR	RCC PLLI2S configuration register (RCC_PLLI2SCFGR), chapter 5.3.23 Access: no wait state, word, half-word and byte access
CRCC_PLLSAICFGR	RCC PLLSAI configuration register (RCC_PLLSAICFGR), chapter 5.3.24 Access: no wait state, word, half-word and byte access
CRCC_SSCGR	RCC spread spectrum clock generation register (RCC_SSCGR), chapter 5.3.22 Access: no wait state, word, half-word and byte access
►CRTCRegisters	(CRC) module register structure
CRTC_ALRMAR	RTC alarm A register, chapter 32.6.7
CRTC_ALRMASSR	RTC alarm a sub second register, chapter 32.6.17
CRTC_ALRMBR	RTC alarm B register, chapter 32.6.8
CRTC_ALRMBSSR	RTC alarm b sub second register, chapter 32.6.18
CRTC_BKPxR	RTC backup register, chapter 32.6.20
CRTC_CALR	RTC calibration register, chapter 32.6.15
CRTC_CR	RTC Control register, chapter 32.6.3
►CRTC_DR	RTC Date register, chapter 32.6.2
CFields
CRTC_ISR	RTC initialization and status register, chapter 32.6.4
CRTC_OR	RTC option register, chapter 32.6.19
CRTC_PRER	RTC prescale register, chapter 32.6.5
CRTC_SHIFTR	RTC shift control register, chapter 32.6.11
CRTC_SSR	RTC sub second register, chapter 32.6.10
CRTC_TAMPCR	RTC tamper configuration register, chapter 32.6.16
►CRTC_TR	RTC Time register, chapter 32.6.1
CFields
CRTC_TSDR	RTC timestamp date register, chapter 32.6.13
CRTC_TSSSR	RTC time stamp sub second register, chapter 32.6.14
CRTC_TSTR	RTC timestamp time register, chapter 32.6.12
CRTC_WPR	RTC write protection register, chapter 32.6.9
CRTC_WUTR	RTC wakeup timer register, chapter 32.6.6
►CSCBRegisters	System Control Block (SCB) register structure
CSCB_ACTLR	Auxiliary Control Register (ACTLR) on page 4-11
CSCB_AIRCR	Application Interrupt and Reset Control Register (AIRCR) on page 4-17
CSCB_BFAR	BusFault Address Register (BFAR) on page 4-31
CSCB_CCR	Configuration and Control Register (CCR) on page 4-20 Access: word access
CSCB_CCSIDR	Cache Size ID Register (CCSIDR) on page 4-39
►CSCB_CFSR	Configurable Fault Status Register (CFSR) on page 4-25 Access: byte, half-word and word access
CSCB_CFSR_BFSR
CSCB_CFSR_MMFSR
CSCB_CFSR_UFSR
CSCB_CLIDR	Cache Level ID Register (CLIDR) on page 4-37
CSCB_CPACR	Coprocessor Access Control Register (CPACR) on page 4-56
CSCB_CPUID	CPUID Base Register (CPUID) on page 4-13
CSCB_CSSELR	Cache Size Selection Register (CSSELR) on page 4-40
CSCB_CTR	Cache Type Register (CTR) on page 4-38
CSCB_DCOSetWay	Data cache operations by set-way (DCISW, DCCSW, DCCISW) on page 4-62
CSCB_DFSR	Debug Fault Status Register (DFSR)
CSCB_HFSR	HardFault Status Register (HFSR) on page 4-31
CSCB_ICSR	Interrupt Control and State Register (ICSR) on page 4-14
CSCB_MMFAR	MemManage Fault Address Register (MMFAR) on page 4-31
CSCB_SCR	System Control Register (SCR) on page 4-20 Access: word access
CSCB_SHCSR	System Handler Control and State Register (SHCSR) on page 4-24 Access: word access
CSCB_SHPR1	System Handler Priority Register 1 (SHPR1) on page 4-23 Access: byte, half-word and word access
CSCB_SHPR2	System Handler Priority Register 2 (SHPR2) on page 4-23 Access: byte, half-word and word access
CSCB_SHPR3	System Handler Priority Register 3 (SHPR3) on page 4-23 Access: byte, half-word and word access
CSCB_VTOR	Vector Table Offset Register (VTOR) on page 4-17
►CSDMMCRegisters	SD/SDIO/MMC card host interface (SDMMC) module register structure
CMASK
►CSDMMC_CLKCR	39.8.2 SDMMC clock control register (SDMMC_CLKCR)
Cfields
►CSDMMC_CMD	39.8.4 SDMMC command register (SDMMC_CMD)
Cfields
►CSDMMC_DCTRL	39.8.9 SDMMC data control register (SDMMC_DCTRL)
Cfields
►CSDMMC_ICR	39.8.12 SDMMC interrupt clear register (SDMMC_ICR)
Cfields
CSDMMC_POWER
►CSDMMC_STA	39.8.11 SDMMC status register (SDMMC_STA)
Cfields
►CSPIRegisters	Serial peripheral interface(SPI) module register structure
CSPIx_CR1	SPI control register 1 (SPIx_CR1), chapter 35.9.1
CSPIx_CR2	SPI control register 2 (SPIx_CR2), chapter 35.9.2
CSPIx_CRCPR	SPI CRC polynomial register (SPIx_CRCPR) , chapter 35.9.5
CSPIx_DR	SPI data register (SPIx_DR), chapter 35.9.4
CSPIx_I2SCFGR	SPIx_I2S configuration register (SPIx_I2SCFGR), chapter 35.9.8
CSPIx_I2SPR	SPIx_I2S prescaler register (SPIx_I2SPR), chapter 35.9.9
CSPIx_RXCRCR	SPI Rx CRC register (SPIx_RXCRCR) , chapter 35.9.7
CSPIx_SR	SPI status register (SPIx_SR), chapter 35.9.3
CSPIx_TXCRCR	SPI Tx CRC register (SPIx_TXCRCR) , chapter 35.9.8
►CSYSCFGRegisters	System configuration controller (SYSCFG) register structure
CSYSCFG_CBR	SYSCFG Compensation cell control register
CSYSCFG_CMPCR
CSYSCFG_EXTICR1	SYSCFG external interrupt configuration registers 2
CSYSCFG_EXTICR2	SYSCFG external interrupt configuration registers 3
CSYSCFG_EXTICR3	SYSCFG external interrupt configuration registers 4
CSYSCFG_EXTICR4	SYSCFG Class B register
CSYSCFG_MEMRMP	SYSCFG memory remap register SYSCFG peripheral mode configuration register
CSYSCFG_PMC	SYSCFG external interrupt configuration registers 1
►CSYSTICKRegisters	System Tick (SYSTICK) register structure
CSYST_CALIB	SysTick Calibration Value Register (SYST_CALIB) on page 4-35
CSYST_CSR	SysTick Control and Status Register (SYST_CSR) on page 4-33
CSYST_CVR	SysTick Current Value Register (SYST_CVR) on page 4-35
CSYST_RVR	SysTick Reload Value Register (SYST_RVR) on page 4-34
►CTIMRegisters	Timer (TIM) register structure
CTIMx_AF1	TIM1/TIM8 alternate function option register 1 (TIMx_AF1), chapter 25.4.24
CTIMx_AF2	TIM1/TIM8 alternate function option register 2 (TIMx_AF2), chapter 25.4.25
CTIMx_ARR	TIMx auto-reload register (TIMx_ARR), chapter 25.4.12 The value can be 32 bit or 16 bit based on the timer
CTIMx_BDTR	TIM1/TIM8 break and dead-time register (TIMx_BDTR), chapter 25.4.18
►CTIMx_CCER	TIMx capture/compare enable register (TIMx_CCER), chapter 25.4.9
CCCER_IC
CCCER_OC
►CTIMx_CCMR1	TIMx capture/compare mode register 1 (TIMx_CCMR1), chapter 25.4.7
CCCMR1_IC
CCCMR1_OC
►CTIMx_CCMR2	TIMx capture/compare mode register 2 (TIMx_CCMR2), chapter 25.4.8
CCCMR2_IC
CCCMR2_OC
►CTIMx_CCMR3	TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3), chapter 25.4.21
CCCMR3_OC
CTIMx_CCR5	TIM1/TIM8 capture/compare register 5 (TIMx_CCR5), chapter 25.4.22
CTIMx_CCRx	TIMx capture/compare register x (TIMx_CCRx), chapter 25.4.14 to 17 and 23 (note that TIMxCCR5 has some extra bits, see below) The value can be 32 bit or 16 bit based on the timer
►CTIMx_CNT	TIMx counter (TIMx_CNT), chapter 25.4.10
CBit16
CBit32
CTIMx_CR1	TIMx control register 1 (TIMx_CR1), chapter 25.4.1
CTIMx_CR2	TIM1x control register 2 (TIMx_CR2), chapter 25.4.2
CTIMx_DCR	TIMx DMA control register (TIMx_DCR), chapter 25.4.19
CTIMx_DIER	TIMx DMA/interrupt enable register (TIMx_DIER), chapter 25.4.4
CTIMx_DMAR	TIM1/TIM8 DMA address for full transfer (TIMx_DMAR), chapter 25.4.20
CTIMx_EGR	TIM1x event generation register (TIMx_EGR), chapter 25.4.6
CTIMx_OR	TIMx option register 1 (TIMx_OR), chapter 26.4.19, chapter 26.4.20 and chapter 27.5.11 Combination of both registers because they are located on the same address
CTIMx_PSC	TIMx prescaler (TIMx_PSC), chapter 25.4.11
CTIMx_RCR	TIM1/TIM8 repetition counter register (TIMx_RCR), chapter 25.4.13
CTIMx_SMCR	TIMx slave mode control register (TIMx_SMCR), chapter 25.4.3
CTIMx_SR	TIMx status register (TIMx_SR), chapter 25.4.5
►CUsartRegisters	(USART) module register structure
CUSART_BRR	Baud rate register (USART Baud rate register), chapter 34.8.4
CUSART_CR1	Control register 1 (USART Control register 1), chapter 34.8.1
CUSART_CR2	Control register 2 (USART Control register 2), chapter 34.8.2
CUSART_CR3	Control register 3 (USART Control register 3), chapter 34.8.3
CUSART_GTPR	USART Guard time and prescaler register, chapter 34.8.5
CUSART_ICR	USART Interrupt flag clear register , chapter 34.8.9
CUSART_ISR	USART Interrupt and status register , chapter 34.8.8
CUSART_RDR	USART receive data register, chapter 34.8.10
CUSART_RQR	USART Request register , chapter 34.8.7
CUSART_RTOR	USART Receiver timeout register , chapter 34.8.6
CUSART_TDR	USART transmit data register, chapter 34.8.11
►CUsbRegisters	(USB) module register structure
COTG_CID	41.15.13 OTG core ID register (OTG_CID)
►COTG_DIEPTXF0_HNPTXFSIZ	41.15.10 OTG host non-periodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0)
Cdevice
Chost
COTG_GAHBCFG	USB_OTG_Core_Registers, chapter 41.15.1-41.15.16
COTG_GCCFG	41.15.12 OTG general core configuration register (OTG_GCCFG)
COTG_GINTMSK	41.15.7 OTG interrupt mask register (OTG_GINTMSK)
COTG_GINTSTS	41.15.6 OTG core interrupt register (OTG_GINTSTS)
COTG_GRSTCTL	41.15.5 OTG reset register (OTG_GRSTCTL)
COTG_GRXSTSP	41.15.8 OTG receive status debug read/OTG status read and pop registers (OTG_GRXSTSR/OTG_GRXSTSP)
COTG_GUSBCFG	41.15.4 OTG USB configuration register (OTG_GUSBCFG)
COTG_HCCHAR	USB_OTG_Host_Channel_Registers, chapter 41.15.25-41.15.30
COTG_HCFG	USB_OTG_Host_Mode_Registers, chapter 41.15.17-41.15.24
COTG_HCINT	41.15.27 OTG host channel x interrupt register (OTG_HCINTx) (x = 0..15[HS] / 11[FS], where x = Channel number)
COTG_HCINTMSK	41.15.28 OTG host channel x interrupt mask register (OTG_HCINTMSKx) (x = 0..15[HS] / 11[FS], where x = Channel number)
COTG_HCTSIZ	41.15.29 OTG host channel x transfer size register (OTG_HCTSIZx) (x = 0..15[HS] / 11[FS], where x = Channel number)
COTG_HFNUM	41.15.20 OTG host frame number/frame time remaining register (OTG_HFNUM)
COTG_HPRT	41.15.24 OTG host port control and status register (OTG_HPRT)
►COTG_HPTXFSIZ	41.15.15 OTG host periodic transmit FIFO size register (OTG_HPTXFSIZ)
Cfields
CREG
CUSB_Core
CUSB_Host
CUSB_HostChannel
►CWWDGRegisters	(WWDG) system window satchdog module register structure
CWWDG_CFR	Configuration register (WWDG_CFR), chapter 31.4.2
CWWDG_CR	Control register (WWDG_CR), chapter 31.4.1
CWWDG_SR	Status register (WWDG_SR), chapter 31.4.3
CCoreCortexM7
CSystemMemoryMap	Definition of hardware memory map
CADCModuleAddress	Enumeration of the available ADC modules identifiers
CDMAModuleAddress	Enumeration of the available DMA modules identifiers
CDMAStreamModuleAddress	Enumeration of the available DMA stream modules identifiers
CGPIOModuleAddress	Enumeration of the available GPIO modules identifiers
CI2CModuleAddress	Enumeration of the available I2C modules identifiers
CI2SModuleAddress	Enumeration of the available I2S modules identifiers
CLTDCLayerModuleAddress	Enumeration of the available LTDC modules identifiers
CUsartModuleAddress	Enumeration of the available USART/UART modules on STM32F769
CSPIModuleAddress	Enumeration of the available SPI modules on STM32F769
CTIMModuleAddress	Enumeration of the available TIM modules identifiers
CCANModuleAddress	Enumeration of the available CAM modules on STM32F769
CSDMMCModuleAddress	Enumeration of the available SDMMC modules on STM32F769
CUSBModuleAddress	Enumeration of the available USB OTG modules on STM32F769
CTiming
CStatus	HAL Status structures definition
CLock	HAL Lock structures definition
CFunctionalState	Functional State, can be used for registers with bit access
CEdgePolarity	Edge Polarity
►Nstm32h730
►Nmock
CMockADC	Mock implementation for the ADC module
CMockCRCheck	Mock implementation for the CRC module
CMockDMA	Mock implementation for the DMA module
CMockDMAMUX	Mock implementation for the DMAMUX module
►CMockFLASH	Mock implementation for the FLASH module
CFlashSectorAddress
CMockGPIO	Mock implementation for a GPIO module
CMockI2C	Mock implementation for a I2C module
CMockMPU	Mock implementation for the MPU module
CMockNVIC	Mock implementation for the NVIC module
CMockOSPI	Mock implementation for the OSPI module
CMockOSPIM	Mock implementation for the OSPIM module
CMockPWR	Mock implementation for PWR
CMockRCC	Mock implementation for the RCC module
CMockRTC	Mock implementation for the RTC module
CMockSYSCFG	Mock implementation for SYSCFG controller
CMockSYSTICK	Mock implementation for SYSTICK module
CMockTIM	Mock implementation for the TIM module
CMockUSART	Mock implementation for the USART module
CMockCoreCortexM7	Mock implementation for the CoreCortexM7 module
CSTM32H730Mock	Mocking object which stores all relevant information for STM32H730 HAL
►Nperipherals
►CADC	Analog Digital Converter (ADC) module
CInitCommonStruct	ADC init common structure definition
CInitRegularChannelStruct	ADC init regular channel structure definition
CInitRegularStruct	ADC init regular structure definition
CInitStruct	ADC init structure definition
►CCRCheck	Cyclic redundancy check calculation (CRC)module
CInitStruct	CRC Init structure definition
►CDMA	Direct memory access controller DMA Reference: ST_CortexM7_STM32H730_TRM_Rev4.pdf Chapter 8
CConfigStruct	DMA Config structure definition
CInitStruct	DMA Init structure definition
CDMAMUX	Direct memory access controller DMA Reference: ST_CortexM7_STM32H730_TRM_Rev4.pdf Chapter 8
►CFLASH	Embedded FLASH memory (FLASH)
CFlashSectorAddress	Flash sector addresses
►CGPIO	General Purpose I/O module Reference: ST_CortexM7_STM32H730_TRM_Rev2.pdf Chapter 13
CInitStruct	GPIO configuration structure definitions
CPinDefinitionStruct	Structur for PinDefinition
►CI2C	Inter-Integrated Circuit I2C module Reference: ST_CortexM7_STM32H730_TRM_Rev2.pdf Chapter 52
CInitStruct
CRxStruct
CTxRxStruct
CTxStruct
►CMPU	Memory Protection Unit (MPU) Reference : ARM Cortex-M7 Generic User Guide DUI0646B.pdf Chapter 4.6 Optional Memory Protection Unit
CRegionConfigStruct	MPU Region structure definition
CNVIC	Nested vectored interrupt controller (NVIC) peripheral module
►COSPI	(OSPI) module register structure
CAutoPollingInitStructure	OSPI AutoPolling structure definition
CCommandInitStruct	OSPI Command structure definition
CInitStruct	OSPI Init structure definition
CMemoryMapInitStructure	OSPI Memory Mapped mode structure definition
►COSPIM	(OSPIM) module register structure
CInitStruct	OSPIM struct used for init method
CPnCRStruct	OSPIM struct used to set the PCR register for port n
CPWR	Power controller module Reference: ST_CortexM7_STM32F767_TRM_Rev2.pdf Chapter 4
►CRCC	Reset and clock control (RCC) peripheral module
CClockConfigStruct	RCC System, AHB and APB busses clock configuration structure
COscillatorConfigStruct	RCC Oscillator configuration structure definition
CPLLConfigStruct	PLL (phase locked loop) configuration structure definition
►CRTC	Real time Clock module Reference: ST_CortexM7_STM32H730_TRM_Rev2.pdf Chapter 51
CAMPM	Enumeration for AM/PM selection
CClockSource	Enumeration for RTC ClockSource Selection
CDateStruct	RTC time structure definitions
CDayLightSaving	Enumeration for RTC DayLight Saving Definition
CHourFormat	Enumeration for hour format
CInitStruct	RTC config structure definition
CMonth	Enumeration for month day units
COutPutPolarity	Enumeration for RTC Output Polarity Definition - not used in current implementation
COutputSelection	Enumeration for Output selection - not used in current implementation
CTampPreChargeDuration	Enumeration for RTC_TAMP precharge duration - not used in current implementation
CTimeStruct	RTC time structure definitions
CWakeupClockSelection	Enumeration for Wakeup Clock selection - not used in current implementation
CWeekday	Enumeration for weekday units
CSYSCFG	System Configuration Controller
CSYSTICK	System timer (SysTick) peripheral modul Reference: ARM Cortex-M7 Generic User Guide DUI0646B Chapter 4.4
►CTIM	Timer (TIMx) peripheral module
CClkSrcInitStruct	TIM clock init structure definition
CEncInitStruct	Encoder Configuration structure defintion
CICInitStruct	Input Capture Configuration structure defintion
CInitStruct	TIM Init structure definition
CMasterInitStruct	Master Configuration structure defintion
COCInitStruct	Output Compare configuration structure definition
CSlaveInitStruct	Slave configuration structure
►CUSART	Usart/Uart peripheral module Reference: ST_CortexM7_STM32H730_TRM_Rev2.pdf Chapter 53
CInitStruct	Usart Init structure definition
►Nregisters
►CADC12Registers	Analog digital converter (ADC) register structure
CADC_AWDxCR	ADC analog watchdog x configuration register (ADC_AWDxCR) (x=2.3), chapter 28.6.19, 28.6.20
CADC_CALFACT	ADC calibration factors register (ADC_CALFACT), chapter 28.6.26
CADC_CALFACT2	ADC calibration factor register 2 (ADC_CALFACT2), chapter 28.6.27
CADC_CFGR	ADC configuration register (ADC_CFGR), chapter 28.6.4
CADC_CFGR2	ADC configuration register 2 (ADC_CFGR2), chapter 28.6.5
CADC_CR	ADC control register (ADC_CR), chapter 28.6.3
CADC_DIFSEL	ADC differential mode selection register (ADC_DIFSEL), chapter 28.6.25
CADC_DR	ADC reguler data register (ADC_DR), chapter 28.6.15
CADC_HTRx	ADC watchdog threshold register x (ADC_HTRx) (x=1-3), chapter 28.6.10, 28.6.22, 28.6.24
CADC_IER	ADC interrupt enable register (ADC_IER), chapter 28.6.2
CADC_ISR	ADC interrupt and status register (ADC_ISR), chapter 28.6.1
CADC_JDRy	ADC injected channel y data register (ADC_JDRy), chapter 28.6.18
CADC_JSQR	ADC injected sequence register (ADC_JSQR), chapter 28.6.16
CADC_LTRx	ADC watchdog threshold register x (ADC_LTRx) (x=1-3), chapter 28.6.9, 28.6.21, 28.6.23
CADC_OFRy	ADC injected channel y offset register (ADC_OFRy), chapter 28.6.17
CADC_PCSEL	ADC channel preselection register (ADC_PCSEL), chapter 28.6.8
CADC_SMPR1	ADC sample time register 1 (ADC_SMPR1), chapter 28.6.6
CADC_SMPR2	ADC sample time register 2 (ADC_SMPR2), chapter 28.6.7
CADC_SQR1	ADC regular sequence register 1 (ADC_SQR1), chapter 28.6.11
CADC_SQR2	ADC regular sequence register 2 (ADC_SQR2), chapter 28.6.12
CADC_SQR3	ADC regular sequence register 3 (ADC_SQR3), chapter 28.6.13
CADC_SQR4	ADC regular sequence register 4 (ADC_SQR4), chapter 28.6.14
►CADC3Registers	Analog digital converter (ADC) register structure
CADC_AWDxCR	ADC analog watchdog x configuration register (ADC_AWDxCR) (x=2.3), chapter 29.6.19, 29.6.20
CADC_CALFACT	ADC calibration factors register (ADC_CALFACT), chapter 29.6.22
CADC_CFGR	ADC configuration register (ADC_CFGR), chapter 29.6.4
CADC_CFGR2	ADC configuration register 2 (ADC_CFGR2), chapter 29.6.5
CADC_CR	ADC control register (ADC_CR), chapter 29.6.3
CADC_DIFSEL	ADC differential mode selection register (ADC_DIFSEL), chapter 29.6.21
CADC_DR	ADC reguler data register (ADC_DR), chapter 29.6.15
CADC_IER	ADC interrupt enable register (ADC_IER), chapter 29.6.2
CADC_ISR	ADC interrupt and status register (ADC_ISR), chapter 29.6.1
CADC_JDRy	ADC injected channel y data register (ADC_JDRy), chapter 29.6.18
CADC_JSQR	ADC injected sequence register (ADC_JSQR), chapter 29.6.16
CADC_OFRy	ADC injected channel y offset register (ADC_OFRy), chapter 29.6.17
CADC_SMPR1	ADC sample time register 1 (ADC_SMPR1), chapter 29.6.6
CADC_SMPR2	ADC sample time register 2 (ADC_SMPR2), chapter 29.6.7
CADC_SQR1	ADC regular sequence register 1 (ADC_SQR1), chapter 29.6.11
CADC_SQR2	ADC regular sequence register 2 (ADC_SQR2), chapter 29.6.12
CADC_SQR3	ADC regular sequence register 3 (ADC_SQR3), chapter 29.6.13
CADC_SQR4	ADC regular sequence register 4 (ADC_SQR4), chapter 29.6.14
CADC_TR1	ADC watchdog threshold register x (ADC_LTRx) (x=1-3), chapter 29.6.8
CADC_TR2	ADC watchdog threshold register x (ADC_HTRx) (x=1-3), chapter 29.6.9
CADC_TR3	ADC watchdog threshold register 3 (ADC_TR3), 29.6.10
►CADCCommonRegisters	ADC Common module (ADCCOMMON) register structure
CADCx_CCR	ADC common control register (ADCx_CCR) (x=1/2), chapter 28.7.2 ADC common control register (ADCx_CCR) (x=3), chapter 29.7.2
CADCx_CDR	ADC common regular data register for dual and triple modes (ADCx_CDR) (x=1/2), chapter 28.7.3 does not exist for ADC3
CADCx_CDR2	ADC common regular data register for 32-bit dual mode (ADCx_CDR2) (x=1/2), chapter 28.7.4 does not exist for ADC3
CADCx_CSR	ADC Common status register (ADCx_CSR) (x=1/2), chapter 28.7.1 ADC Common status register (ADCx_CSR) (x=3), chapter 29.7.1
►CCRCRegisters	(CRC) module register structure
CCRC_CR	Control register (CRC_CR), chapter 21.4.3
CCRC_DR	Data register (CRC_DR), chapter 21.4.1
CCRC_IDR	Independent data register (CRC_IDR), chapter 21.4.2
CCRC_INIT	Initial CRC value (CRC_INIT), chapter 21.4.4
CCRC_POL	CRC polynomial (CRC_POL), chapter 21.4.5
►CDMAMUXRegisters	Direct memory access request multiplexer (DMAMUX) register structure
►CDMAMUX_CFR	DMAMUX1 request line interrupt clear flag register (DMAMUX1_CFR), chapter 17.6.5 DMAMUX2 request line interrupt clear flag register (DMAMUX2_CFR), chapter 17.6.6
CDMAMUX1_CFR
CDMAMUX2_CFR
►CDMAMUX_CSR	DMAMUX1 request line interrupt channel status register (DMAMUX1_CSR), chapter 17.6.3 DMAMUX2 request line interrupt channel status register (DMAMUX2_CSR), chapter 17.6.4
CDMAMUX1_CSR
CDMAMUX2_CSR
►CDMAMUX_CxCR	DMAMUX1 request line multiplexer channel x configuration register (DMAMUX1_CxCR) for x=0:15, chapter 17.6.1 DMAMUX2 request line multiplexer channel x configuration register (DMAMUX2_CxCR) for x=0:7, chapter 17.6.2
CDMAMUX1_CxCR
CDMAMUX2_CxCR
►CDMAMUX_RGCFR	DMAMUX1 request generator interrupt clear flag register (DMAMUX1_RGCFR), chapter 17.6.11 DMAMUX2 request generator interrupt clear flag register (DMAMUX2_RGCFR), chapter 17.6.12
CDMAMUX1_RGCFR
CDMAMUX2_RGCFR
►CDMAMUX_RGSR	DMAMUX1 request generator interrupt status register (DMAMUX1_RGSR), chapter 17.6.9 DMAMUX2 request generator interrupt status register (DMAMUX2_RGSR), chapter 17.6.10
CDMAMUX1_RGSR
CDMAMUX2_RGSR
►CDMAMUX_RGxCR	DMAMUX1 request generator channel x configuration register (DMAMUX1_RGxCR) for x=0:7, chapter 17.6.7 DMAMUX2 request generator channel x configuration register (DMAMUX2_RGxCR) for x=0:7, chapter 17.6.8
CDMAMUX1_RGxCR
CDMAMUX2_RGxCR
►CDMARegisters	Direct memory access (DMA) register structure
CDMA_HIFCR	DMA low interrupt flag clear register (DMA_HIFCR), chapter 15.5.4
CDMA_HISR	DMA high interrupt status register (DMA_HISR), chapter 15.5.2
CDMA_LIFCR	DMA low interrupt flag clear register (DMA_LIFCR), chapter 15.5.3
CDMA_LISR	DMA low interrupt status register (DMA_LISR), chapter 15.5.1
►CDMAStreamRegisters	Direct memory access (DMA) stream register structure
CDMA_SxCR	DMA stream x configuration register (DMA_SxCR) (x = 0..7), chapter 15.5.5
CDMA_SxFCR	DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7), chapter 15.5.10
CDMA_SxM0AR	DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7), chapter 15.5.8
CDMA_SxM1AR	DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7), chapter 15.5.9
CDMA_SxNDTR	DMA stream x number of data register (DMA_SxNDTR) (x = 0..7), chapter 15.5.6
CDMA_SxPAR	DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7), chapter 15.5.7
►CFLASHRegisters	Flash (FLASH) registers
CFLASH_ACR	FLASH Access Control Register Access: no wait state, word, half-word and byte access
CFLASH_BOOT_CUR	FLASH register boot address for Arm� Cortex�-M7 core Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_BOOT_PRG	FLASH register boot address for Arm� Cortex�-M7 core Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_CCR	FLASH clear control register Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_CR	FLASH control register Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_CRCCR	FLASH CRC control register Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_CRCDATAR	FLASH CRC data register Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_CRCEADDR	FLASH CRC end address register Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_CRCSADDR	FLASH CRC start address register Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_ECC_FAR	FLASH ECC fail address Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_KEYR	FLASH Key register Access: no wait state, word access
CFLASH_OPTCCR	FLASH option clear control register Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_OPTCR	FLASH option status register Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_OPTKEYR	FLASH Option key register Access: no wait state, word access
CFLASH_OPTSR2_CUR	FLASH option status register 2 Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_OPTSR2_PRG	FLASH option status register 2 Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_OPTSR_CUR	FLASH option control register Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_OPTSR_PRG	FLASH option status register Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_PRAR_CUR	FLASH protection address Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_PRAR_PRG	FLASH protection address Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_SCAR_CUR	FLASH secure address Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_SCAR_PRG	FLASH secure address Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_SR	FLASH status register Access: no wait state, word, half-word and byte access
CFLASH_WPSN_CUR	FLASH write sector protection Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
CFLASH_WPSN_PRG	FLASH write sector protection Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access
►CGPIORegisters	General purpose input/output module (GPIO) register structure
CGPIOx_AFRH	GPIO alternate function high register (GPIOx_AFRH) (x =A to H, J, K), chapter 11.4.10
CGPIOx_AFRL	GPIO port configuration lock register (GPIOx_LCKR) (x =A to H, J, K), chapter 11.4.8
CGPIOx_BSRR	GPIO port bit set/reset register (GPIOx_BSRR) (x =A to H, J, K), chapter 11.4.7
CGPIOx_IDR	GPIO port input data register (GPIOx_IDR) (x =A to H, J, K), chapter 11.4.5
CGPIOx_MODER	GPIO port mode register (GPIOx_MODER) (x =A to H, J, K), chapter 11.4.1
CGPIOx_ODR	GPIO port output data register (GPIOx_ODR) (x =A to H, J, K), chapter 11.4.6
CGPIOx_OSPEEDR	GPIO port output speed register (GPIOx_OSPEEDR) (x =A to H, J, K), chapter 11.4.3
CGPIOx_OTYPER	GPIO port output type register (GPIOx_OTYPER) (x =A to H, J, K), chapter 11.4.2
CGPIOx_PUPDR	GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x =A to H, J, K), chapter 11.4.4
►CI2CRegisters	(IC2) module register structure
CI2C_CR1	Control register 1 (I2C_CR1), chapter 52.7.1
CI2C_CR2	Control register 2 (I2C_CR2), chapter 52.7.2
CI2C_ICR	Interrupt clear register (I2C_ICR), chapter 52.7.8
CI2C_ISR	Interrupt and status register (I2C_ISR), chapter 52.7.7
►CI2C_OAR1	Own address 1 register (I2C_OAR1), chapter 52.7.3
CAddressMode10Bit
CAddressMode7Bit
CI2C_OAR2	Own address 2 register (I2C_OAR2), chapter 52.7.4
CI2C_PECR	PEC register (I2C_PECR), chapter 52.7.9
CI2C_RXDR	Receive data register (RXDR_RXDR), chapter 52.7.10
CI2C_TIMEOUTR	Timeout register (I2C_TIMEOUTR), chapter 52.7.6
►CI2C_TIMINGR	Timing register (I2C_TIMINGR), chapter 52.7.5
CRegisterfields
CI2C_TXDR	Transmit data register (I2C_TXDR), chapter 52.7.11
►CMPURegisters	(MPU) register structure - Memory Protection Unit
CMPU_CTRL	MPU Control Register, Chapter 4.6.2
CMPU_RASR	MPU Region Attribute and Size Register, Chapter 4.6.5 Access: word access
CMPU_RBAR	MPU Region Base Address Register, Chapter 4.6.4
CMPU_RNR	MPU Region Number Register, Chapter 4.6.3
CMPU_TYPE	MPU Type Register, Chapter 4.6.1 The MPU_TYPE register indicates whether the optional MPU is present, and if so, how many regions it supports
►CNVICRegisters	(NVIC) register structure
CNVIC_STIR	Software Trigger Interrupt Register (NVIC_STIR), chapter 4.2.8, page 4-8
►COSPIMRegisters	(Octo-SPI I/O Manager) module register structure
COCTOSPIM_CR	OCTOSPIM control register (OCTOSPIM_CR), chapter 26.4.1
COCTOSPIM_PnCR	OCTOSPIM port n configuration register (OCTOSPIM_PnCR) (n=1 to 2), chapter 26.4.2
►COSPIRegisters	(Octo-SPI) module register structure
COCTOSPI_ABR	OCTOSPI alternate bytes registers (OCTOSPI_ABR), chapter 25.6.17
COCTOSPI_AR	OCTOSPI address register (OCTOSPI_AR), chapter 25.6.9
►COCTOSPI_CCR	OCTOSPI communication configuration register (OCTOSPI_CCR), chapter 25.6.14
CFields
COCTOSPI_CR	OCTOSPI control register (OCTOSPI_CR), chapter 25.6.1
COCTOSPI_DCR1	OCTOSPI device configuration register (OCTOSPI_DCR1), chapter 25.6.2
COCTOSPI_DCR2	OCTOSPI device configuration register (OCTOSPI_DCR2), chapter 25.6.3
COCTOSPI_DCR3	OCTOSPI device configuration register (OCTOSPI_DCR3), chapter 25.6.4
COCTOSPI_DCR4	OCTOSPI device configuration register (OCTOSPI_DCR4), chapter 25.6.5
COCTOSPI_DLR	OCTOSPI data length register (OCTOSPI_DLR), chapter 25.6.8
COCTOSPI_DR	OCTOSPI data register (OCTOSPI_DR), chapter 25.6.10
COCTOSPI_FCR	OCTOSPI flag clear register (OCTOSPI_FCR), chapter 25.6.7
COCTOSPI_HLCR	OCTOSPI HyperBus latency configuration register (OCTOSPI_HLCR), chapter 25.6.27
COCTOSPI_IR	OCTOSPI instruction register (OCTOSPI_IR), chapter 25.6.16
COCTOSPI_LPTR	OCTOSPI low-power timeout register (OCTOSPI_LPTR), chapter 25.6.18
COCTOSPI_PIR	OCTOSPI polling interval register (OCTOSPI_PIR), chapter 25.6.13
COCTOSPI_PSMAR	OCTOSPI polling status match register (OCTOSPI_PSMAR), chapter 25.6.12
COCTOSPI_PSMKR	OCTOSPI polling status mask register (OCTOSPI_PSMKR), chapter 25.6.11
COCTOSPI_SR	OCTOSPI status register (OCTOSPI_SR), chapter 25.6.6
COCTOSPI_TCR	OCTOSPI timing configuration register (OCTOSPI_TCR), chapter 25.6.15
COCTOSPI_WABR	OCTOSPI write alternate bytes register (OCTOSPI_WABR), chapter 25.6.26
COCTOSPI_WCCR	OCTOSPI write communication configuration register (OCTOSPI_WCCR), chapter 25.6.23
COCTOSPI_WIR	OCTOSPI write instruction register (OCTOSPI_WIR), chapter 25.6.25
COCTOSPI_WPABR	OCTOSPI wrap alternate bytes register (OCTOSPI_WPABR), chapter 25.6.22
COCTOSPI_WPCCR	OCTOSPI wrap communication configuration register (OCTOSPI_WPCCR), chapter 25.6.19
COCTOSPI_WPIR	OCTOSPI wrap instruction register (OCTOSPI_WPIR), chapter 25.6.21
COCTOSPI_WPTCR	OCTOSPI wrap timing configuration register (OCTOSPI_WPTCR), chapter 25.6.20
COCTOSPI_WTCR	OCTOSPI write timing configuration register (OCTOSPI_WTCR), chapter 25.6.24
►CPWRRegisters	(PWR) register structure
CPWR_CPUCR	PWR CPU control register (PWR_CPUCR), chapter 6.8.5
CPWR_CR1	PWR power control register (PWR_CR1), chapter 6.8.1
CPWR_CR2	PWR power control/status register 2 (PWR_CR2) (PWR_CR2), chapter 6.8.3
CPWR_CR3	PWR power control/status register 3 (PWR_CR3), chapter 6.8.4
CPWR_CSR1	PWR power control/status register (PWR_CSR1), chapter 6.8.2
CPWR_D3CR	PWR D3 domain control register (PWR_D3CR), chapter 6.8.6
CPWR_WKUPCR	PWR wakeup clear register (PWR_WKUPCR), chapter 6.8.7
CPWR_WKUPEPR	PWR wakeup enable and polarity register (PWR_WKUPEPR), chapter 6.8.9
CPWR_WKUPFR	PWR wakeup flag register (PWR_WKUPFR), chapter 6.8.8
►CRCCRegisters	(RCC) register structure
CRCC_AHB1ENR	RCC AHB1 peripheral clock register (RCC_AHB1ENR)), chapter 8.7.40 Access: no wait state, word, half-word and byte access
CRCC_AHB1LPENR	RCC AHB1 Sleep clock register (RCC_AHB1LPENR), chapter 8.7.49 Access: no wait state, word, half-word and byte access
CRCC_AHB1RSTR	RCC AHB1 peripheral reset register (RCC_AHB1RSTR), chapter 8.7.28 Access: no wait state, word, half-word and byte access
CRCC_AHB2ENR	RCC AHB2 peripheral clock enable register (RCC_AHB2ENR), chapter 8.7.41 Access: no wait state, word, half-word and byte access
CRCC_AHB2LPENR	RCC AHB2 Sleep clock register (RCC_AHB2LPENR), chapter 8.7.50 Access: no wait state, word, half-word and byte access
CRCC_AHB2RSTR	RCC AHB2 peripheral reset register (RCC_AHB2RSTR), chapter 8.7.29 Access: no wait state, word, half-word and byte access
CRCC_AHB3ENR	RCC AHB3 peripheral clock enable register (RCC_AHB2ENR), chapter 8.7.39 Access: no wait state, word, half-word and byte access
CRCC_AHB3LPENR	RCC AHB3 Sleep clock register (RCC_AHB3LPENR), chapter 8.7.48 Access: no wait state, word, half-word and byte access
CRCC_AHB3RSTR	RCC AHB3 peripheral reset register (RCC_AHB3RSTR), chapter 8.7.27 Access: no wait state, word, half-word and byte access
CRCC_AHB4ENR	RCC AHB4 clock register (RCC_AHB4ENR), chapter 8.7.42 Access: no wait state, word, half-word and byte access
CRCC_AHB4LPENR	RCC AHB4 Sleep clock register (RCC_AHB4LPENR), chapter 8.7.51 Access: no wait state, word, half-word and byte access
CRCC_AHB4RSTR	RCC AHB4 peripheral reset register (RCC_AHB4RSTR), chapter 8.7.30 Access: no wait state, word, half-word and byte access
CRCC_APB1HENR	RCC APB1 clock register (RCC_APB1HENR), chapter 8.7.45 Access: no wait state, word, half-word and byte access
CRCC_APB1HLPENR	RCC APB1 High Sleep clock register (RCC_APB1HLPENR), chapter 8.7.54 Access: no wait state, word, half-word and byte access
CRCC_APB1HRSTR	RCC APB1 peripheral reset register (RCC_APB1HRSTR), chapter 8.7.33 Access: no wait state, word, half-word and byte access
CRCC_APB1LENR	RCC APB1 clock register (RCC_APB1LENR), chapter 8.7.44 Access: no wait state, word, half-word and byte access
CRCC_APB1LLPENR	RCC APB1 Low Sleep clock register (RCC_APB1LLPENR), chapter 8.7.53 Access: no wait state, word, half-word and byte access
CRCC_APB1LRSTR	RCC APB1 peripheral reset register (RCC_APB1LRSTR), chapter 8.7.32 Access: no wait state, word, half-word and byte access
CRCC_APB2ENR	RCC APB2 clock register (RCC_APB2ENR), chapter 8.7.46 Access: no wait state, word, half-word and byte access
CRCC_APB2LPENR	RCC APB2 Sleep clock register (RCC_APB2LPENR), chapter 8.7.55 Access: no wait state, word, half-word and byte access
CRCC_APB2RSTR	RCC APB2 peripheral reset register (RCC_APB2RSTR), chapter 8.7.34 Access: no wait state, word, half-word and byte access
CRCC_APB3ENR	RCC APB3 clock register (RCC_APB3ENR), chapter 8.7.43 Access: no wait state, word, half-word and byte access
CRCC_APB3LPENR	RCC APB3 Sleep Clock Register (RCC_APB3LPENR), chapter 8.7.52 Access: no wait state, word, half-word and byte access
CRCC_APB3RSTR	RCC APB3 peripheral reset register (RCC_APB3RSTR), chapter 8.7.31 Access: no wait state, word, half-word and byte access
CRCC_APB4ENR	RCC APB4 clock register (RCC_APB4ENR), chapter 8.7.47 Access: no wait state, word, half-word and byte access
CRCC_APB4LPENR	RCC APB4 Sleep clock register (RCC_APB4LPENR), chapter 8.7.56 Access: no wait state, word, half-word and byte access
CRCC_APB4RSTR	RCC APB4 peripheral reset register (RCC_APB4RSTR), chapter 8.7.35 Access: no wait state, word, half-word and byte access
CRCC_BDCR	RCC backup domain control register (RCC_BDCR), chapter 8.7.25 Access: no wait state, word, half-word and byte access
CRCC_CFGR	RCC clock configuration register (RCC_CFGR), chapter 8.7.6 Access: 0 <= wait state <= 2, word, half-word and byte access
CRCC_CICR	RCC clock source interrupt clear register (RCC_CICR), chapter 8.7.24 Access: no wait state, word, half-word and byte access
CRCC_CIER	RCC clock source interrupt enable register (RCC_CIER), chapter 8.7.22 Access: no wait state, word, half-word and byte access
CRCC_CIFR	RCC clock source interrupt flag register (RCC_CIFR), chapter 8.7.23 Access: no wait state, word, half-word and byte access
CRCC_CR	RCC source control register (RCC_CR), chapter 8.7.2 Access: no wait state, word, half-word and byte access
CRCC_CRRCR	RCC clock recovery RC register (RCC_CRRCR), chapter 8.7.4 Access: no wait state, word, half-word and byte access
CRCC_CSICFGR	RCC CSI configuration register (RCC_CSICFGR), chapter 8.7.5 Access: no wait state, word, half-word and byte access
CRCC_CSR	RCC clock control & status register (RCC_CSR), chapter 8.7.26 Access: 0 <= wait state <= 3, word, half-word and byte access
CRCC_D1CCIPR	RCC domain 1 kernel clock configuration register (RCC_D1CCIPR), chapter 8.7.18 Access: no wait state, word, half-word and byte access
CRCC_D1CFGR	RCC domain 1 clock configuration register (RCC_D1CFGR), chapter 8.7.7 Access: 0 <= wait state <= 2, word, half-word and byte access
CRCC_D2CCIP1R	RCC domain 2 kernel clock configuration register (RCC_D2CCIP1R), chapter 8.7.19 Access: no wait state, word, half-word and byte access
CRCC_D2CCIP2R	RCC domain 2 kernel clock configuration register (RCC_D2CCIP2R), chapter 8.7.20 Access: no wait state, word, half-word and byte access
CRCC_D2CFGR	RCC domain 2 clock configuration register (RCC_D2CFGR), chapter 8.7.8 Access: 0 <= wait state <= 2, word, half-word and byte access
CRCC_D3AMR	RCC D3 Autonomous mode register (RCC_D3AMR), chapter 8.7.37 Access: no wait state, word, half-word and byte access
CRCC_D3CCIPR	RCC domain 3 kernel clock configuration register (RCC_D3CCIPR), chapter 8.7.21 Access: no wait state, word, half-word and byte access
CRCC_D3CFGR	RCC domain 3 clock configuration register (RCC_D3CFGR), chapter 8.7.9 Access: 0 <= wait state <= 2, word, half-word and byte access
CRCC_GCR	RCC global control register (RCC_GCR), chapter 8.7.36 Access: no wait state, word, half-word and byte access
CRCC_HSICFGR	RCC HSI configuration register (RCC_HSICFGR), chapter 8.7.3 Access: no wait state, word, half-word and byte access
CRCC_PLL1DIVR	RCC PLL1 dividers configuration register (RCC_PLL1DIVR), chapter 8.7.12 Access: no wait state, word, half-word and byte access
CRCC_PLL1FRACR	RCC PLL1 fractional divider register (RCC_PLL1FRACR), chapter 8.7.13 Access: no wait state, word, half-word and byte access
CRCC_PLL2DIVR	RCC PLL2 dividers configuration register (RCC_PLL2DIVR), chapter 8.7.14 Access: no wait state, word, half-word and byte access
CRCC_PLL2FRACR	RCC PLL2 fractional divider register (RCC_PLL2FRACR), chapter 8.7.15 Access: no wait state, word, half-word and byte access
CRCC_PLL3DIVR	RCC PLL3 dividers configuration register (RCC_PLL3DIVR), chapter 8.7.16 Access: no wait state, word, half-word and byte access
CRCC_PLL3FRACR	RCC PLL1 fractional divider register (RCC_PLL1FRACR), chapter 8.7.17 Access: no wait state, word, half-word and byte access
CRCC_PLLCFGR	RCC PLLs Configuration Register (RCC_PLLCFGR), chapter 8.7.11 Access: no wait state, word, half-word and byte access
CRCC_PLLCKSELR	RCC PLLs clock source selection register (RCC_PLLCKSELR), chapter 8.7.10 Access: no wait state, word, half-word and byte access
CRCC_RSR	RCC reset status register (RCC_RSR), chapter 8.7.38 Access: no wait state, word, half-word and byte access
►CRTCRegisters	(CRC) module register structure
CRTC_ALRMAR	RTC alarm A register, chapter 51.7.7
CRTC_ALRMASSR	RTC alarm a sub second register, chapter 51.7.17
CRTC_ALRMBR	RTC alarm B register, chapter 51.7.8
CRTC_ALRMBSSR	RTC alarm b sub second register, chapter 51.7.18
CRTC_BKPxR	RTC backup register, chapter 51.7.20
CRTC_CALR	RTC calibration register, chapter 51.7.15
CRTC_CR	RTC Control register, chapter 51.7.3
►CRTC_DR	RTC Date register, chapter 51.7.2
CFields
CRTC_ISR	RTC initialization and status register, chapter 51.7.4
CRTC_OR	RTC option register, chapter 51.7.19
CRTC_PRER	RTC prescale register, chapter 51.7.5
CRTC_SHIFTR	RTC shift control register, chapter 51.7.11
CRTC_SSR	RTC sub second register, chapter 51.7.10
CRTC_TAFCR	RTC tamper and alternate function configuration register, chapter 51.7.16
►CRTC_TR	RTC Time register, chapter 51.7.1
CFields
CRTC_TSDR	RTC timestamp date register, chapter 51.7.13
CRTC_TSSSR	RTC time stamp sub second register, chapter 51.7.14
CRTC_TSTR	RTC timestamp time register, chapter 51.7.12
CRTC_WPR	RTC write protection register, chapter 51.7.9
CRTC_WUTR	RTC wakeup timer register, chapter 51.7.6
►CSCBRegisters	System Control Block (SCB) register structure
CSCB_ACTLR	Auxiliary Control Register (ACTLR) on page 4-13
CSCB_AIRCR	Application Interrupt and Reset Control Register (AIRCR) on page 4-17
CSCB_BFAR	BusFault Address Register (BFAR) on page 4-31
CSCB_CCR	Configuration and Control Register (CCR) on page 4-20 Access: word access
CSCB_CCSIDR	Cache Size ID Register (CCSIDR) on page 4-39
►CSCB_CFSR	Configurable Fault Status Register (CFSR) on page 4-26 Access: byte, half-word and word access
CSCB_CFSR_BFSR
CSCB_CFSR_MMFSR
CSCB_CFSR_UFSR
CSCB_CLIDR	Cache Level ID Register (CLIDR) on page 4-37
CSCB_CPACR	Coprocessor Access Control Register (CPACR) on page 4-56
CSCB_CPUID	CPUID Base Register (CPUID) on page 4-14
CSCB_CSSELR	Cache Size Selection Register (CSSELR) on page 4-40
CSCB_CTR	Cache Type Register (CTR) on page 4-38
CSCB_DCOSetWay	Data cache operations by set-way (DCISW, DCCSW, DCCISW) on page 4-62
CSCB_DFSR	Debug Fault Status Register (DFSR)
CSCB_HFSR	HardFault Status Register (HFSR) on page 4-31
CSCB_ICSR	Interrupt Control and State Register (ICSR) on page 4-15
CSCB_MMAR	MemManage Fault Address Register (MMAR) on page 4-31
CSCB_SCR	System Control Register (SCR) on page 4-19 Access: word access
CSCB_SHCSR	System Handler Control and State Register (SHCSR) on page 4-25 Access: word access
CSCB_SHPR1	System Handler Priority Register 1 (SHPR1) on page 4-22 Access: byte, half-word and word access
CSCB_SHPR2	System Handler Priority Register 2 (SHPR2) on page 4-23 Access: byte, half-word and word access
CSCB_SHPR3	System Handler Priority Register 3 (SHPR3) on page 4-24 Access: byte, half-word and word access
CSCB_VTOR	Vector Table Offset Register (VTOR) on page 4-16
►CSYSCFGRegisters	System configuration controller (SYSCFG) register structure
CSYSCFG_ADC2ALT
CSYSCFG_CCCR
CSYSCFG_CCCSR
CSYSCFG_CCVR
CSYSCFG_CFGR
CSYSCFG_EXTICR1
CSYSCFG_EXTICR2
CSYSCFG_EXTICR3
CSYSCFG_EXTICR4
CSYSCFG_PKGR
CSYSCFG_PMCR
CSYSCFG_UR0
CSYSCFG_UR11
CSYSCFG_UR12
CSYSCFG_UR13
CSYSCFG_UR14
CSYSCFG_UR15
CSYSCFG_UR16
CSYSCFG_UR17
CSYSCFG_UR18
CSYSCFG_UR2
CSYSCFG_UR3
CSYSCFG_UR4
CSYSCFG_UR5
CSYSCFG_UR6
CSYSCFG_UR7
►CSYSTICKRegisters	System Tick (SYSTICK) register structure
CSYST_CALIB	SysTick Calibration Value Register (SYST_CALIB) on page 4-35
CSYST_CSR	SysTick Control and Status Register (SYST_CSR) on page 4-33
CSYST_CVR	SysTick Current Value Register (SYST_CVR) on page 4-35
CSYST_RVR	SysTick Reload Value Register (SYST_RVR) on page 4-34
►CTIMRegisters	Timer (TIM) register structure
CTIMx_AF1	TIM1/TIM8 alternate function option register 1 (TIMx_AF1), chapter 43.4.26, 43.4.28 TIM2,3,5 and TIM23/24: Only register field ETRSEL is used
CTIMx_AF2	TIM1/TIM8 alternate function option register 2 (TIMx_AF2), chapter 43.4.27, 43.4.29
CTIMx_ARR	TIMx auto-reload register (TIMx_ARR) The value can be 32 bit or 16 bit based on the timer
CTIMx_BDTR	TIM1/TIM8 break and dead-time register (TIMx_BDTR), chapter 43.4.20
►CTIMx_CCER	TIMx capture/compare enable register (TIMx_CCER), chapter 43.4.11 Only bit 0,1 and 3 used for TIM 13/14, see chapter 45.5.7 In the description of the CCxP, CCxNE and CCxNP Bits, one can see that the functionality is different in input capture mode
CCCER_IC
CCCER_OC
►CTIMx_CCMR1	TIMx capture/compare mode register 1 (TIMx_CCMR1), chapter 43.4.7, 43.4.8
CCCMR1_IC
CCCMR1_OC
►CTIMx_CCMR2	TIMx capture/compare mode register 2 (TIMx_CCMR2), chapter 43.4.9, 43.4.10
CCCMR2_IC
CCCMR2_OC
►CTIMx_CCMR3	TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3), chapter 43.4.23
CCCMR3_OC
CTIMx_CCR5	TIM1/TIM8 capture/compare register 5 (TIMx_CCR5), chapter 43.4.24
CTIMx_CCRx	TIMx capture/compare register x (TIMx_CCRx) The value can be 32 bit or 16 bit based on the timer
►CTIMx_CNT	TIMx counter (TIMx_CNT) TIM 1/8 - 16 bit: see chapter 43.4.12 TIM2/3/4/5/23/24 - 32 bit: see chapter 44.4.13 TIM12 - 16 bit: see chapter 45.4.10 TIM13/14 - 16 bit: see chapter 45.5.8 TIM15 - 16 bit: see chapter 46.5.10 TIM16/17 - 16 bit: see chapter 46.6.9 TIM6/7 - 16 bit: see chapter 47.4.6
CBit16
CBit31_WithRemapping
CBit32_NoRemapping
CTIMx_CR1	TIMx control register 1 (TIMx_CR1), chapter 43.4.1
CTIMx_CR2	TIM1x control register 2 (TIMx_CR2), chapter 43.4.2 Bit 0, 2 and 8-31 only for TIM1 and TIM8
CTIMx_DCR	TIMx DMA control register (TIMx_DCR), chapter 43.4.21
CTIMx_DIER	TIMx DMA/interrupt enable register (TIMx_DIER), chapter 43.4.4 only bit 0 and 1 used for TIM 13/14
CTIMx_DMAR	TIM1/TIM8 DMA address for full transfer (TIMx_DMAR) TIM 1/8 - 32 bit: see chapter 43.4.22 TIM2/3/4/5/23/24 - 16 bit: see chapter 44.4.21 TIM12 - not used TIM13/14 - not used TIM15 - 16 bit: see chapter 46.5.18 TIM16/17 - 16 bit: see chapter 46.6.16 TIM6/7 - not used
CTIMx_EGR	TIM1x event generation register (TIMx_EGR), chapter 43.4.6 Only bit 0 and 1 used for TIM 13/14
CTIMx_PSC	TIMx prescaler (TIMx_PSC), chapter 43.4.13
CTIMx_RCR	TIM1/TIM8 repetition counter register (TIMx_RCR), chapter 43.4.15
CTIMx_SMCR	TIMx slave mode control register (TIMx_SMCR), chapter 43.4.3
CTIMx_SR	TIMx status register (TIMx_SR), chapter 43.4.5 Only bit 0,1 and 9 used for TIM 13/14
CTIMx_TISEL	TIM1 timer input selection register (TIM1_TISEL), chapter 43.4.03, 43.4.31
►CUsartRegisters	(USART) module register structure
CUSART_BRR	Baud rate register (USART Baud rate register), chapter 53.7.5
►CUSART_CR1	Control register 1 (USART Control register 1), chapter 53.7.1 & 53.7.2
CUSART_CR1_FIFO_DIS
CUSART_CR1_FIFO_EN
►CUSART_CR2	Control register 2 (USART Control register 2), chapter 53.7.3
CUSART_CR2_ADD0ADD1
CUSART_CR2_ADD8
CUSART_CR3	Control register 3 (USART Control register 3), chapter 53.7.4
CUSART_GTPR	USART Guard time and prescaler register, chapter 53.7.6
CUSART_ICR	USART Interrupt flag clear register , chapter 53.7.11
►CUSART_ISR	USART Interrupt and status register , chapter 53.7.9 & 53.7.10
CUSART_ISR_FIFO_DIS
CUSART_ISR_FIFO_EN
CUSART_PRESC	USART prescaler register, chapter 53.7.14
CUSART_RDR	USART receive data register, chapter 53.7.12
CUSART_RQR	USART Request register , chapter 53.7.8
CUSART_RTOR	USART Receiver timeout register , chapter 53.7.7
CUSART_TDR	USART transmit data register, chapter 53.7.13
CCoreCortexM7
CSystemMemoryMap	Definition of hardware memory map
▼Nlib
►Nalarms
CAlarmSenderIfc	Interface to send an alarm message to activate or deactivate a given alarm
CFlagAlarm	Activates the given alarms if the flag is set and deactivates it when the flag is cleared
CRangeAlarm	Activates the given alarms if the value is outside a defined range
CRangeAlarmWithDelay	Activates the given alarms if the value is outside the range longer as the given delay
CRangeAlarmWithHysteresis	Activates the given alarms if the value is outside the set range
►Ncrypto
CEllipticCurveDSA	This class provides the functions to use the elliptic curve digital signature algorithm
CSha256Hash	Provides the functions required to calculate a SHA-256 hash
►Nremoting
CCRC16CheckFailedCallbackIfc	Callback to handle a failed CRC16 check
CDataFrame	Representation of a package of data that gets transmitted e.g
CDataFrameCRC16CheckReceiveLayer	This layer checks incoming data frames for crc errors
CDataFrameCRC16CheckSendLayer	This layer checks incoming data frames for crc errors
CDataFrameQueueOverflowListenerIfc	DataFrameQueueOverflowListenerIfc
CDataFrameSyncReceiveLayer	This layer receives a byte stream from a lower layer and tries to generate data frames out of the byte streams data
CDataFrameSyncSendLayer	This layer appends frame end chars to mark the the end of a data frame
CDataReceiverIfc	DataReceiverIfc
CDataSenderIfc	DataSenderIfc
CRemoteObjectAbs	Provides an abstract base class for all remote object implementations
CRemoteObjectCallbackTemplate	Defines a remote object template to serialize and deserialize a protocol and send them to a callback function
CRemoteObjectIfc	Classes that implement this interface provide a generic mechanism to exchange data with a remoting peer
CRemoteObjectSignalTemplate	Defines a remote object template to serialize and deserialize a protocol
CRemoteObjectTemplate	Defines a remote object template to serialize and deserialize a protocol and send them directly to a PortOut
►CRemotePools	RemotePools
CDataFrameData	Struct to save frame data
CRemotingReceiveService	Service for remote objects to receive data from another remote object
CRemotingSendService	Service for remote objects to send data to another remote object
CRemotingSendServiceIfc	Interface for the remoting sending service (allows remote objects to initiate the send by themselves)
CRemotingServiceBase	Provides the base Class for RemotingSendService and RemotingReceiveService, which implements the RemotingServiceIfc
CRemotingServiceIfc	Interface for the RemotingService
►Nsrecconverter
CDataRecord	DataRecord
CSRecConverter	The SRecConverter is used to read a Motorola srecord binary file
►Nstrings
CStringConversion	String conversion class
▼Nos
►Nfreertos
CFreeRTOSMailbox	A FreeRTOS specific Mailbox
►Nlinux
►Ngmock
CMockCpuStatistics	Cpu statistics mock implementation
CMockFileIo	File io mock implementation
CMockMemoryStatistics	Memory statistics mock implementation
CMockNetworkInterface	Network interface mock implementation
CMockOS	Mock manager, which will be the entry point for all MockObjects
CMockProcess	Process mock implementation
CMockSerialPort	Serial port mock implementation
CMockSystemTime	System time mock implementation
CMockThread	Mock thread implementation
CCpuStatistics	Provides functions to read out the current CPU usage
CFileIo	Provide file access functions
CMemoryStatistics	Provides functions to read out current memory usage information
CNetworkInterface	Provides functions to
CProcess	Helper class to call process specific functions
CRamUsageInfo	Helper class to store RAM usage information
CSerialPort	Provides functions to transmit serial port data
CSerialPortConfig	Maintains configuration information of a serial port
CSystemTime	Provides functions to read the current system time
CThread	Provides a thread instance toghether with the infrastructure required to stop the thread as well as some synchronization primitives that can be used to synchronize access to shared data
CThreadHelper	Helper to apply scheduling policies on a thread instance
CThreadSchedulingParams	Provides the parameters required to setup the scheduling of a thread
▼NUnitTestActiveParts
CTestEventArgs	Serializable test data used within tests with two uint32_t parameters
▼NunitTestHelper
CActivePartHelper	Helper for sending messages to an active part
CMockTestBase	Base class for all UnitTests which use the mocking infrastructure
CTestAssertActionHandler	Helper class for initializing the AssertActionManager
CTestBase	Test base class
CTestUtil	Provides utility functions for TestClasses
C__fpscr
C__infinity_un
C__nan_un
Cenv87
Cenvxmm
Cfenv_t
Cfpacc87
Cieee_double_shape_type
Cieee_extended_shape_type
Cieee_float_shape_type
Cieee_quad_shape_type
CIEEEd2bits
CIEEEf2bits
CIEEEl2bits
Csave87
Csavefpu
Csavexmm
Cxmmacc